International Business Machines Corporation

Globalfoundries Inc.

Todd Alan Inglett

Charles J Archer

Joseph D Ratterman

Brian E Smith

Michael A Blocksome

Andrew Thomas Tauferner

Robert William Wisniewski

Thomas M Gooding

Patrick Joseph McCarthy

Ahmad A Faraj

Alan G Gara

Michael B Mundy

Michael K Gschwind

Valentina Salapura

Dong Chen

Paul William Coteus

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Amanda Peters

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Yoonho Park

Charles David Wait

Sameer Kumar

James Anthony Marcella

George L Chiu

Krishnan Sugavanam

Gerard Vincent Kopcsay

Bryan Savoye Rosenburg

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Rudolf Adriaan Haring

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Gabor J Dozsa

Ruth Janine Poole

Thomas Edward Musta

Thomas A Liebsch

Brant L Knudson

Ralph E Bellofatto

Peter Boyle

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Hubertus Franke

Hartmut Penner

Daniel A Faraj

Don Darrell Reed

Gordon G Stewart

Thomas A Budnik

Don Reed

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

Methods, apparatus, and products are disclosed for providing full point-to-point communications among compute nodes of an operational group in a global combining network of a parallel computer, each compute node connected to each adjacent compute node in the global combining network through a link, that include: receiving a network packet in a compute node, the network packet specifying a destination compute node; selecting, in dependence upon the destination compute node, at least one of the links for the compute node along which to forward the network packet toward the destination compute node; and forwarding the network packet along the selected link to the adjacent compute node connected to the compute node through the selected link.

Providing full point-to-point communications among compute nodes of an operational group in a global combining network of a parallel computer

Routing data communications packets in a parallel computer that includes compute nodes organized for collective operations. Each compute node including an operating system kernel and a system-level messaging module that is a module of automated computing machinery that exposes a messaging interface to applications. Each compute node including a routing table that specifies, for each of a multiplicity of route identifiers, a data communications path through the compute node. Including to carry out the steps of: receiving in a compute node a data communications packet that includes a route identifier value; retrieving from the routing table a specification of a data communications path through the compute node; and routing, by the compute node, the data communications packet according to the data communications path identified by the compute node's routing table entry for the data communications packet's route identifier value.

Routing data communications packets in a parallel computer

Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the parallel computing system pseudorandomly modify entropy data during broadcast operations through application of arithmetic and/or logic operations. That is, each compute node's ALU may modify the entropy data during broadcasts, thereby mixing, and thus improving, the entropy data with every hop of entropy data packets from one node to another. At each compute node, the respective ALUs may further deposit modified entropy data in, e.g., local entropy pools such that software running on the compute nodes and needing entropy data may fetch it from the entropy pools. In some embodiments, entropy data may be broadcast via dedicated packets or included in unused portions of existing broadcast packets.

Method of entropy randomization on a parallel computer

Methods, apparatus, and products are disclosed for providing point to point data communications among compute nodes in a global combining network of a parallel computer that include: determining a class route identifier available for all of the nodes along a communications path from an origin node to a target node; configuring network hardware of each node along the communications path with routing instructions in dependence upon the available class route identifier and the network's topology; transmitting, by the origin node along the communications path, a network packet to the target node, including encoding the available class route identifier in the network packet; and routing, by the network hardware of each node along the communications path, the network packet to the target node in dependence upon the routing instructions for each node and the available class route identifier.

Providing point to point communications among compute nodes in a global combining network of a parallel computer

Method for performing an operation, the operation including, responsive to receiving a file system request at a file system, retrieving a first entropy pool element from the file system, and inserting, at the file system, the first entropy pool element into a network packet sent from the file system responsive to the file system request.

Method of entropy distribution on a parallel computer

Method, system, and computer program product for performing an operation, the operation including, responsive to receiving a file system request at a file system, retrieving a first entropy pool element from the file system, and inserting, at the file system, the first entropy pool element into a network packet sent from the file system responsive to the file system request.

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Managing a direct memory access ('DMA') injection first-in-first-out ('FIFO') messaging queue in a parallel computer, including: inserting, by a messaging unit management module, a DMA message descriptor into the injection FIFO messaging queue; determining, by the messaging unit management module, the number of extra slots in an immediate messaging queue required to store DMA message data associated with the DMA message descriptor; and responsive to determining that the number of extra slots in the immediate message queue required to store the DMA message data is greater than one, inserting, by the messaging unit management module, a number of DMA dummy message descriptors into the injection FIFO messaging queue, wherein the number of DMA dummy message descriptors is at least as many as the number of extra slots in the immediate messaging queue that are required to store the DMA message data.

Managing a direct memory access ('DMA') injection first-in-first-out ('FIFO') messaging queue in a parallel computer

Methods, apparatuses, and computer program products for utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer are provided. Embodiments include a kernel assigning a memory space of a hardware thread of an application processing core to a kernel administration hardware thread of a kernel processing core. A kernel administration hardware thread is configured to advance the hardware thread to a next memory space associated with the hardware thread in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread. Embodiments also include the kernel administration hardware thread executing an instruction within the assigned memory space.

Utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer

A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system.

Method to utilize cores in different operating system partitions

Enabling a Light-Weight Kernel (LWK) to run in a virtualized environment on a Full-Weight Kernel (FWK), in one aspect, may include replacing a FWK loader, e.g., FWK's dynamic library loader or linker, with a LWK library on a first computing entity for an application allocated to run on one or more second computing entities. The LWK library may be enabled to initialize the one or more second computing entities and associated memory allocated to run the application under the LWK library. The LWK library may be enabled to manage the one or more second computing entities and said associated memory and resources needed by the application.

Method to embed a light-weight kernel in a full-weight kernel to provide a heterogeneous execution environment

A parallel computer system adds entropy to improve the quality of random number generation by using parity errors as a source of entropy because parity errors are influenced by external forces such as cosmic ray bombardment, alpha particle emission, and other random or near-random events. By using parity errors and associated information to generate entropy, the quality of random number generation in a parallel computer system is increased.

Adding entropy for improved random number generation in a computer system

Growing community of inventors

Rochester, MN, United States of America

Todd Alan Inglett