Micron Technology Incorporated

Micron Semiconductor, Inc.

Round Rock Research, LLC

Todd A Merritt

Donald M Morgan

Troy A Manning

Brett L Williams

Paul S Zagar

Timothy B Cowles

Greg A Blodgett

Kevin J Ryan

Jeffrey S Mailloux

Robert Michael Walker

Kevin G Duesman

Jeffrey P Wright

J Thomas Pawlowski

George B Raad

Shubneesh Batra

Michael Amiel Shore

Hua Zheng

Dan Skinner

Huy Thanh Vo

Layne G Bunker

Vikram K Bollu

Salman Akram

Brent Keeth

Adrian E Ong

Brian L Johnson

Yantao Ma

Kurt D Beigel

Patrick J Mullarkey

Chris G Martin

Howard Kirsch

Douglas John Cutter

Fan Ho

Michael D Chaine

Brett M Debenham

Kim M Pierce

Hal W Butler

J Wayne Thompson

Dien S Luong

Eric J Smith

Richard A Mecier

Nicholas VanHeel

Stephen L Casper

Charles L Ingalls

Tae Hyoung Kim

Joseph C Sher

Zhong-Yi Xia

Danial S Dean

Brian J Ladner

Frank Alejano

Paul M Prew

Nick Van Heel

Jonathan L Gossi

Greg A Blogett

Yu-Wen Huang

Mingshiang Wang

Robert Walker

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Memory having internal processors and data communication methods in memory

Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.

Degradation signaling for a memory device

Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Apparatuses and methods for adjusting deactivation voltages

Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

Line driver circuits, methods, and apparatuses

Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.

Distributed write data drivers for burst access memories

Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling.

Coupling cancellation scheme

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.

Output buffer having inherently precise data masking

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them.

Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation

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Boise, ID, United States of America

Todd A Merritt