Intel Corporation

Boston University

Todd A Hinck

Zuoguo Wu

Mahesh U Wagh

Venkatraman Iyer

Gerald S Pasdast

David M Lee

Narasimha R Lanka

Matthew E Becker

Zibing Yang

John B Halbert

Aaron K Martin

Sanka Ganesan

Andrew W Martwick

Qiang Zhang

Alan Fiedler

Timothy D Wig

Larry R Tate

Georgios Asmanis

Allyn E Hubbard

Howard I Cohen

Jose Robins

In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to 'center' the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional 'eye' phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a &#x201c;victim&#x201d; lane, with adjacent &#x201c;aggressor&#x201d; lanes having a complementary bit pattern.

Method, apparatus, system for centering in a high performance interconnect

An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle.

System interconnect for integrated circuits

Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces

An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Non-blocking power management for on-package input/output architectures

In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Receiver for recovering and retiming electromagnetically coupled data

In at least one embodiment an apparatus is provided that includes an electromagnetic coupler probe to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler probe and to provide recovered sampled electromagnetic signals. Other embodiments may be described and claimed.

Apparatus to receive signals from electromagnetic coupler

A tunable current mode integrator for low-frequency continuous-time filters that requires a reduced amount of area when implemented in an integrated circuit (IC). The integrator includes input and output transistors, and cross-coupled current mirrors, integration capacitors, and operational transconductance amplifiers (OTAs) that form a feedback structure with the input transistors. Input currents are converted to small current swings within the OTAs, and are subsequently integrated by the capacitors. Resulting integrated voltages are converted to output currents by the output transistors.

Tunable current-mode integrator for low-frequency filters

Growing community of inventors

Arlington, MA, United States of America

Todd A Hinck