Texas Instruments Corporation

Other

Tod David Wolf

Alan Gatherer

David J Hoyle

Jonathan H Shiell

Eric Biscondi

Antonio F Mondragon-Torres

Patrick W Bosshart

Ching-Yu Hung

Yaqi Cheng

Pedro Ramon Gelabert

Trudy D Stetzler

William J Ebel, Sr

Armelle Laine

David R Shoemaker

William J Ebel

Logic circuitry and corresponding software instructions for performing functions within the FL function of a Kasumi cipher. An RLAX logic circuit includes a bit-wise AND function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLAX program instruction. An RLOX logic circuit includes a bit-wise OR function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLOX program instruction. Plural instances of the logic circuits can be implemented in parallel, to simultaneously operate upon plural data blocks.

Kasumi cipher executable instructions and circuitry

A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m&#xd7;j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

Method and system for decoding low density parity check codes

A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.

Local memories with permutation functionality for digital signal processors

This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.

Viterbi traceback initial state index initialization for partial cascade processing

This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index with the selected decision bits from the unused ACS units. This invention uses the modified final maximum state index as the initial conditions for the k&#x2212;1 traceback shift register. This invention also uses the final maximum state index to mask the generated pretraceback decision bits generated from the last block of ACS units.

Viterbi pretraceback for partial cascade processing

Operands () that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined () whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted () to produce respectively corresponding adjusted operand values () for use in a binary arithmetic operation.

Using quadrant shifting to facilitate binary arithmetic with two's complement operands

MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations. The cascade architecture limits the required number of max* blocks which compute the logarithm of a sum of exponentials as part of the BCJR method.

Cascade map decoder and method

This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.

Turbo decoder prolog reduction

The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

Concurrent memory control for turbo decoders

A turbo decoder in which a sliding-block MAP decoder pipelines the forward-propagating and backward-propagating computations.

MAP decoding with parallelized sliding window processing

A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a signal-to-noise ratio based on the mean and variance of soft-output estimates. The decoding process is aborted based on a comparison of the generated signal-to-noise ratio to a predetermined threshold.

Turbo decoder stopping criterion improvement

This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.

Turbo decoder extrinsic normalization

According to one embodiment of the present invention, a digital hearing device is disclosed. The digital hearing aid includes a microphone for receiving sound, which may include an analog signal. The analog signal is converted by a first converter into a digital signal. Filters are provided to divide the digital signal into multiple signal parts. A signal processor may be provided for each signal part, and performs signal processing on its respective signal part. An adder adds the output of the signal processors, which results in a processed digital signal. A second converter converts the processed digital signal back into an analog signal. A speaker then outputs the analog signal. According to another embodiment of the present invention, a method for enhancing sound is provided. The method includes the steps of: (1) receiving sound containing an analog signal; (2) converting the analog signal to a digital signal; (3) dividing the digital signal into signal parts; (4) performing signal processing on the signal parts; (5) adding the processed signal parts, resulting in a processed digital signal; (6) converting the processed digital signal to a processed analog signal; and (7) outputting the processed analog signal. According to another embodiment of the present invention, a digital hearing system is provided. The digital hearing system includes at least one hearing device and a central processing unit. The hearing device includes a microphone for receiving sound that includes an analog signal, a transmitter for transmitting the analog signal, and a receiver for receiving a processed analog signal. The central processing unit includes a receiver for receiving the analog signal from the hearing device, a signal processor for processing the signal, and a transmitter for transmitting the processed signal to the hearing device.

Digital hearing device, method and system

The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor. A subtractor forms the difference between inputs A and B. The sign of this difference controls a multiplexer selection of the max function maximum of inputs A and B. The difference is applied to a lookup table built to handle both positive and negative inputs. The look up table output is summed with with the difference to form the MAX star result. The size of the lookup table is selected to match the required resolution.

DSP instruction for turbo decoding

A combinatorial polynomial multiplier for Galois Field 256 arithmetic utilizes fewer components than an iterative Galois Field 256 arithmetic multiplier and operates 8 times faster. The combinatorial multiplier employs AND and XOR functions and operates in a single clock cycle. It can reduce the number of transistors required for the Galois Field 256 arithmetic multiplier for a Reed-Solomon decoder by almost 90%.

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Richardson, TX, United States of America

Tod David Wolf