International Business Machines Corporation

Tobias Ulrich Bergmann

Oliver Benke

Tobias Webel

Scott Barnett Swaney

Guenter Gerwig

Felix O Beier

Terence Patrick Purcell

Thomas Gentner

Ulrich Weiss

Dennis Butterstein

Klaus Theurich

Ralf Ludewig

Muhammad Usman Karim Khan

Dominic Röhm

A method for maintaining a memory replica of a primary computer system to be used by an alternate computer system is provided. Provided are detecting changes performed on a memory device of the primary computer system by software executed on the primary computer system. Also provided is monitoring at least one memory controller of the primary computer system; triggering, based on the monitoring, a snapshot creation procedure, the snapshot creation procedure comprising creating a memory snapshot that comprises the detected changes.

Maintaining a memory replica of a primary computer system

A computer-implemented method for seamlessly performing a maintenance operation on a stateful system includes mapping a network address of the stateful system to a primary server that uses a primary database to respond to incoming data requests. In response to receiving a maintenance request, the primary database is replicated to a secondary database of a secondary server. The secondary server is updated according to the maintenance request. The method further includes caching, in a replay buffer of the primary server, incoming data requests during the replicating. After the replicating, the data requests from the replay buffer are executed by the secondary server. Write operations to the primary server are disabled during the replicating, and the network address of the stateful system is mapped to the secondary server. Subsequently, the primary server is updated and reinstated by mapping the network address, and enabling the write operations.

Updating stateful system in server cluster

Embodiments include method, systems and computer program products for compressing instrumentation data. Aspects include defining an intermediate region of memory. Instrumentation data associated with a processing device is received and stored in the intermediate region of the memory. The instrumentation data is compressed in the intermediate region of memory and stored in a sample region of memory.

Hardware accelerated compression of instrumentation data

A method for distributed training in a parameter dataset; the method for at least one coordinating node; a network of at least one distributed node; receiving a parameter dataset from a first distributed node; decrypting the received dataset; training the parameter dataset based on a training data record to obtain a trained parameter dataset; and forwarding the trained parameter dataset to a second distributed node.

Distributed training in a parameter dataset

Methods and systems for generating database statistics. Table statistics in a metadata catalog of a source database system are observed, statistics generation costs utilizing a target database system are estimated, and source statistics generation costs utilizing a source database system are estimated. The statistics generation costs are compared and statistics generation queries by the target database system are triggered in response to the statistics generation costs utilizing the target database system having a predefined relationship with the source statistics generation costs utilizing the source database system. The statistics generation queries are performed by the target database system in response to the triggering by the source database system. The generated statistics are sent from the target database system to the source database system, the table statistics in a metadata catalog are updated based on the generated statistics, and the updated table statistics are used to optimize a query plan.

Offloading statistics collection

Secure operations are performed on encrypted code. A processor in a first operating mode obtains encrypted code. The processor switches from the first operating mode to a second operating mode, and decrypts the encrypted code to obtain decrypted code. The decrypted code is executed, based on the processor being in the second operating mode, to provide a result. The result is encrypted, and the encrypted result is sent to a user, based on the processor switching back to the first operating mode.

Secure operations on encrypted data

Embodiments of the invention are directed to methods for improving performance of a multi-core processor. A non-limiting method includes increasing a first operating frequency to a first elevated operating frequency of a first core of a gang of cores, the gang of cores comprising a plurality of cores of the multi-core processor. The method further includes upon a determination that an operating temperature of the first core is above a threshold temperature, switching processing of a thread from the first core to a second core in the gang of cores. The method further includes reducing the first operating frequency of the first core. The method further includes increasing the operating frequency of the second core to a second elevated operating frequency.

Thread migration and shared cache fencing based on processor core temperature

A method for a continuous mutual extended processor self-test is provided. The method is implemented by a system including a plurality of cores. The system sets an operating condition for the continuous mutual extended processor self-test. An assist processor of the plurality of cores executes a test program that implements the continuous mutual extended processor self-test on a core under test of the plurality of cores. The system determines a pattern and a response during the test program execution and repeats the test program until the test program has finished or failed.

Continuous mutual extended processor self-test

Noise filtering for an incoming signal is provided. The noise filtering method includes executing a transformation operation on the incoming signal by distributing energy corresponding to each of a plurality of components of the incoming signal into a two-dimensional representation. The noise filtering method also includes executing a filtering operation on the plurality of components to determine real objects and remove noise within the incoming signal. The filtering operation utilizing at least one of a plurality of noise detection matrixes based on time, frequency, or direction.

Signal adaptive noise filter

A generator device being configured for generating pseudo random numbers, the generator device comprising a computing device operable for (i) calculating a first hash chain from an initial hash value (H_), the first hash chain comprising a first sequence of M hash values (HA_, HA_, . . . , HA_M); (ii) calculating a second hash chain () comprising a second sequence of M hash values (HB_, HB_, . . . , HB_M) from the initial hash value (H_) and the hash values (HA_, HA_, . . . , HA_M) of the first sequence; and (iii) determining the pseudo random numbers from the hash values (HB_, HB_, . . . , HB_M) of the second sequence. Also disclosed are a method for generating pseudo random numbers and a method for quantum computing secure authentication, as well as a computer program product and a data processing system.

Generating pseudo random numbers for quantum computing secure authentication

Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Error checking using serial collection of error data

A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

Growing community of inventors

Weinstadt, Germany

Tobias Ulrich Bergmann