Infineon Technologies Ag

Qimonda Ag

Tobias Mono

Matthias Goldbach

Uwe Paul Schroeder

Veit Klee

Arnd Scholz

Paul Wensley

Lars Dreeskornfeld

Martin Commons

Paul Schroeder

John Pohl

Frank Jakubowski

Dirk Offenberg

Erhard Landgraf

Sven Schmidbauer

Stefano Parascandola

Michael Stadtmueller

Klaus-Dieter Morhard

Thomas Schafbauer

Nirmal Chaudhary

Stefan Slesazeck

Alfred Sigl

Tim Boescke

Moritz Haupt

Hermann Sachse

Dietmar Henke

Lars Voelkel

Paul Schröder

Dirk Vietzke

Velt Klee

Andreas Von Ehrenwall

Uwe Paul Schröder

An image sensor device includes a pixel. The pixel includes a semiconductor layer having a first surface. A photodiode is formed in the semiconductor layer and is configured to generate charge carriers based on light reaching the photodiode. A storage node is formed in the semiconductor layer, the storage node being arranged so that charge carriers generated in the photodiode are transferred to the storage node. A light-shielding structure is formed in the semiconductor layer and is disposed at least between the first surface of the semiconductor layer and the storage node so as to prevent at least part of the light travelling in the semiconductor layer away from the first surface from reaching the storage node.

Image sensor device

Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described.

Method of making transistor gates with controlled work function

A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Method of manufacturing integrated circuits including a FET with a gate spacer and a fin

The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Method for manufacturing an integrated circuit including a transistor

An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Integrated circuit and method of manufacturing an integrated circuit

A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90&#xb0;, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

Method of forming a doped portion of a semiconductor and method of forming a transistor

The invention relates to a method and an apparatus for the arrangement of contact-making elements of components of an integrated circuit, a computer-readable storage medium and a program element. In the method for the arrangement of contact-making elements of components of an integrated circuit, at least one part of at least one component having a larger extent along a first course direction than along a second course direction, which is orthogonal to the first course direction, and at least one contact-making element assigned to a component having, in cross section, a larger extent along a third course direction than along a fourth course direction, which is orthogonal to the third course direction, the contact-making element is arranged with respect to the assigned component in such a way that the first course direction of the component essentially runs parallel to the third course direction of the contact-making element.

Method and apparatus for the arrangement of contact-making elements of components of an integrated circuit, computer-readable storage medium and program element

Preferably using a positive resist, a resist ridge () is formed in a photosensitive resist () applied on a semiconductor wafer () above a hard mask layer (). The resist ridge () serves as a mask for a subsequent implantation step (). This makes use of an effect whereby the material of the hard mask layer (), in a part () shaded by the resist ridge (), can be etched out selectively with respect to the implanted part (). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack () that is actually to be patterned. From the resist ridge () that has been formed as a line in the photosensitive resist (), in a type of tone reversal, an opening () has been formed in the hard mask layer and a trench () has been formed in the layer/layer stack (). According to the invention, the width () of the resist ridge () is reduced by exposing the resist ridge () to an oxygen plasma (). As a result, it is possible to form a trench () in the hard mask layer () and in the layer/layer stack () the width () of which trench is smaller than the lithographic resolution limit during the lithographic patterning of the resist ().

Method for forming a trench in a layer or a layer stack on a semiconductor wafer

A platefor projection lithography comprising a first opaque regionlocated at the center of the plateand a second opaque regionformed at the outer edgeof the plate. The first and second opaque regions define a light transmissive annular regionThe annular regioncomprises a first light transmissive areathat imparts a first phase shift to light passing therethrough and a second light transmissive areawhich imparts a second phase shift to light passing therethrough.

Method and apparatus for aerial image improvement in projection lithography using a phase shifting aperture

A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Structure for determining edges of regions in a semiconductor wafer

An alternating phase shift mask ( ) and method of manufacturing thereof including assist edges ( ) and ( ) surrounding a main phase edge ( ). Assist edges ( ) and ( ) improve the resolution of the alternating phase shift mask ( ), thus enabling the patterning of smaller size features on a semiconductor wafer.

Resolution enhancement for alternating phase shift masks

Method and apparatus for determining photoresist pattern linearity. The method and apparatus comprises a substrate and a measuring pattern ( ) printed on the substrate comprising a series of parallel lines ( ) having a line width ( ) and having a pre-determined pitch. By magnifying the semiconductor wafer on which the pattern feature ( ) is printed and analyzing the magnified wafer from a top down view, the linearity of the pattern feature ( ) can be determined from the amount of shift in the edges of the pattern feature ( ). By utilizing the method and apparatus for other pattern features, the linearity of the entire pattern can be determined.

Method and apparatus for determining photoresist pattern linearity

A method of providing shallow trench ( ) isolation for a semiconductor wafer ( ). Trenches ( ) are formed within a first semiconductor material ( ) and a pad nitride ( ), leaving a portion of first semiconductor material ( ) and pad nitride ( ) in a region between the trenches ( ). A second semiconductor material ( ) is deposited over the trenches ( ) to fill the trenches ( ) to a height below the first semiconductor material ( ) top surface. A first insulator ( ) is selectively formed over the second semiconductor material ( ). The pad nitride ( ) and a portion of the first semiconductor material ( ) between the trenches ( ) are removed to isolate element regions of the wafer ( ) and form straps ( ) having a low resistance.

Strap resistance using selective oxidation to cap DT poly before STI etch

A nitride hard mask ( ) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches ( ) on a semiconductor wafer ( ). The memory cell deep trenches ( ) are separated from active areas ( ) by a region of substrate ( ). A nitride hard mask ( ) is formed over the semiconductor wafer ( ). The wafer ( ) is patterned with the nitride hard mask ( ), and the wafer ( ) is etched to remove the region of substrate ( ) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask ( ) is used.

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Dresden, Germany

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