Infineon Technologies Ag

Tobias Islinger

Eric Pihet

Harald Zweck

Magnus-Maria Hell

Jens Repp

Maximilian Mangst

Some aspects of the present disclosure relate to a network processor. The network processor includes a system bus, a central processing unit (CPU) coupled to the system bus, a random access memory (RAM) coupled to the CPU via the system bus; a plurality of network ports coupled to the CPU and the RAM; and a network bridge coupled between the CPU and the plurality of network ports. The network bridge includes a first transmit Direct Memory Access (DMA) circuit and a first transmit memory buffer coupled between the first transmit DMA circuit and a first network port, and a receive memory buffer and frame parser hardware arranged between the receive memory buffer and the system bus.

Frame replication and elimination on microcontroller

In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

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Munich, Germany

Tobias Islinger