International Business Machines Corporation

Tobias Gemmeke

Jens Leenstra

Nicolas Maeding

Jochen Preiss

Dieter F Wendel

Harry S Barowski

Thomas Pflueger

Tim Niggemeier

Jason Raymond Baumgartner

Viresh Paruthi

Cedric Lichtenau

Hari Mony

Markus Kaltenbach

Kerstin Claudia Schelm

Kai Oliver Weber

Holger Wetter

Friedrich Schroeder

Jens Kuenzer

Christoph Jaeschke

J Adam Butts

Stefan Bonsels

A binary logic unit to apply any Boolean operation on two input signals (v, v) is described, wherein any Boolean operation to be applied on the input signals (v, v) is defined by a particular combination of well defined control signals (ctl, ctl, ctl, ctl), wherein the input signals (v, v) are used to select a control signal (ctl, ctl, ctl, ctl) as an output signal (v) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (v, v). Furthermore a method to operate such a binary logic unit is described.

Binary logic unit and method to operate a binary logic unit

A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A', B&#x2032;) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A&#x2032;, B&#x2032;) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit () is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.

Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing

A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.

Permute unit and method to operate a permute unit

Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.

Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance

A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M&#x3c;N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N&#x2212;M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.

Method of operand width reduction to enable usage of narrower saturation adder

A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

System and method for scanning sequential logic elements

The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.

Method and system for verifying the equivalence of digital circuits

The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.

Formally deriving a minimal clock-gating scheme

A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.

Circuit design methodology to reduce leakage power

A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit

A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of:

Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit

A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical '1' to verify the sequential equivalence of the transformed netlist.

Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes

A method for reducing leakage current within a register file of a processor is disclosed. The register file within the processor is partitioned into at least two power domains, and each of the two power domains can be powered independently. At least one of the two power domains includes at least as many physical registers as there are architected registers defined in an instruction set architecture of the processor. In response to an occurrence of an idle condition within the processor, all architected register file entries are consolidated into one of power domains that will not be powered off, and the power domains that does not contain any architected register file entries after consolidating are powered off. Afterwards, in response to a detection of an end of the idle condition, all of the power domains are powered back on.

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Stutensee, Germany

Tobias Gemmeke