Intel Corporation

Tobias Brown-Heft

Matthew V Metz

Jack T Kavalieros

Seung Hoon Sung

Uygar E Avci

Shriram Shivaraman

I-Cheng Tung

Devin Merrill

Gilbert W Dewey

Marko Radosavljevic

Ian A Young

Van H Le

Abhishek A Sharma

Noriyuki Sato

Charles C Kuo

Bernhard Sell

Hui Jae Yoo

Nicole K Thomas

Scott Bruce Clendenning

Ashish Verma Penumatcha

Elliot Tan

Nazila Haratipour

Travis W LaJoie

Pei-Hua Wang

Chieh-Jen Ku

Tristan A Tronic

Sou-Chi Chang

Kirby Maxey

Sudarat Lee

Sarah Atanasov

Thoe Michaelos

Che-Yun Lin

Eric Charles Mattson

Charles Mokhtarzadeh

Jason Peck

A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes HfZO, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes HfZO, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.

Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

Fabrication of thin film fin transistor structure

An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

Ferroelectric capacitors and methods of fabrication

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Portland, OR, United States of America

Tobias Brown-Heft