Texas Instruments Corporation

Toan Tran

Henry Litzmann Edwards

Jeffrey R Debord

Hiroaki Niimi

Rajesh B Khamankar

James Joseph Chambers

Douglas Ticknor Grider

Kenneth James Maggio

Ashesh Parikh

Rajiv R Shah

Bradley David Sucher

Jihong Chen

April Gurba

Howard L Tigelaar

David J Myers

Richard L Guldi

Ricky A Jackson

Deepak Arabagatte Ramappa

Husam N Alshareef

Stephen P Sacarisen

Abha Rani Singh

Michael F Brenner

Johnson J Lin

Gene E Blankenship

Steve Thompson

Melissa M Hewson

In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

CMOS-based thermopile with reduced thermal conductance

An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1&#xd7;10cmn-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1&#xd7;10cmp-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Method of forming a CMOS-based thermoelectric device

CMOS-based thermoelectric device with reduced electrical resistance

A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Structures for testing and locating defects in integrated circuits

Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().

Reliable high voltage gate dielectric layers using a dual nitridation process

The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer () on a substrate (), and subjecting the gate dielectric layer () to a nitrogen containing plasma process (), wherein the nitrogen containing plasma process () has a ratio of helium to nitrogen of 3:1 or greater.

Gate dielectric having a flat nitrogen profile and method of manufacture therefor

A metal fuse process that uses a thinner (e.g., 6000 &angst;) oxide ( ) over the top interconnect ( ). The oxide ( ) is removed over the probe pads ( ) for testing but is not removed over the fuses ( ). Because the oxide ( ) is thin at the upper corners of the fuse ( ), the oxide ( ) cracks over the fuse ( ) during a laser pulse ( ). A wet etch is then used to dissolve the exposed fuses ( ).

Optimized metal fuse process

An improved process for manufacturing semiconductor devices (10). The device, which could be a semiconductor wafer, an individual chip, or a device that has integrated within it semiconductor devices, such as a compact disk drive, is placed or held upside down with its working surface (12) open. The device (10) is struck, causing particulates (18) attached to the working surface (12) to fall free of the device. Alternately, the device could be sharply decelerated to apply the shock. Additionally, the device could be held substantially vertical and rotated to use centrifugal force to separate the particulates away from the device.

Method to reduce particulates in device manufacture

A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS gate conductors and a bipolar emitter structure is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes, and another high impurity concentration area which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips. Alignment of electrode metallization patterns is thus less critical.

Integrated bipolar and CMOS transistor with titanium nitride

A process for making a metal fuse link in a MOS or CMOS process which includes depositing a refractory metal or metal alloy over an already deposited multi-level oxide and patterning the deposited metal or metal alloy so that it has a fusing segment between and integral with expanded segments such that the length and cross sectional area of the fusing segment is sufficiently small so that the fusing current therethrough is less than 20 milliamperes. The fuse and surrounding circuitry is covered with a passivation layer and contacts formed in the passivation layer to the expanded segments.

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Rowlett, TX, United States of America

Toan Tran