Altera Corporation

Toan Thanh Nguyen

Thungoc M Tran

Sergey Yuryevich Shumarayev

Chong H Lee

Ramanand Venkata

Arch Zaliznyak

Shoujun Wang

Tim Tri Hoang

Andy Louie Lee

Weiqi Ding

Cameron R McClintock

Brian D Johnson

Stephanie T Tran

Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device ('PLD') or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits

Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment ('PMA') circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks ('CGBs') in each pair of channel groups receives outputs of multiple phased locked loop circuits (&#x201c;PLLs&#x201d;) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (&#x201c;CDR&#x201d;)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.

Multiple channel bonding in a high speed clock network

A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.

Techniques for canceling offsets in differential circuits

A dynamic flip-flop includes a leakage compensation circuit enabling operation over a wide range of frequencies. Nodes of the dynamic flip-flop store the flip-flop's state. The leakage compensation circuit drains leakage currents from these nodes to prevent the node voltage from rising and triggering an erroneous state change when a data signal changes in the middle of the clock cycle. The leakage compensation circuit associated with a node is activated when the node is set to a low logic level voltage. The leakage compensation circuit is adapted to draw a current from a node that compensates for the leakage current supplied to the node. At the least, this current draw is sufficient to prevent the voltage at the node from rising above a state change threshold voltage during the time period between refresh operations.

Leakage compensation in dynamic flip-flop

Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device ('PLD') or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits

Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two output signals including alternating samples of the input signal. Combinational logic circuitry is also provided to produce a clock-data recovery (CDR) signal indicative of the phase of the input signal with respect to a clock signal. The use of differential signals throughout the BBPD timing circuitry provides for the production of a low jitter CDR signal.

Differential bang-bang phase detector (BBPD) with latency reduction

Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.

Integrated circuit serializers with two-phase global master clocks

Techniques are provided for increasing flexibility to I/O banks with respect to supply voltages. Multiple supply voltages can be provided to a bank of I/O pins. Separate I/O pins residing in an I/O bank are driven by buffers that are coupled to different supply voltages. Dedicated I/O pins are driven by buffers with pre-selected supply voltages. The dedicated I/O pins can be grouped together into the same I/O bank providing greater flexibility to drive signals on I/O pins in other I/O banks at different voltages. Also, a dual mode input buffer can drive an input signal to a voltage determined by one of two possible supply voltage levels. In addition, power on reset circuits for an I/O bank can monitor the voltage of two or more supply voltages.

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San Clara, CA, United States of America

Toan Thanh Nguyen