Chartered Semiconductor Manufacturing Ltd (corporation)

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Tjin Tjin Tjoa

Yelehanka Ramachandramurthy Pradeep

Haoren Zhuang

Chit Hwei Ng

Chaw Sing Ho

Matthias Lipinski

O Sung Kwon

Jian Xun Li

Shailendra Mishra

Jie Yu

Kok Wai Chew

Chong Kwang Chang

Young Gun Ko

Shao Fu Sanford Chu

Kelvin Wei Loong Loh

Vijaikumar Chhagan

Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas

A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si N or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.

Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology

A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.

Method of forming spacers of multiple widths

A method of fabricating a gate stack having an endpoint detect layer and a multi-step etch process to prevent damage to a gate dielectric layer. The special endpoint detect layer emits an endpoint signal that allows the etch chemistry to be changed to a more selective polysilicon to oxide ratio to prevent damage to the gate oxide layer. The invention begins by forming a gate dielectric layer over a substrate. We then form an endpoint detect layer over the gate dielectric layer. A gate stack is formed over the bottom silicon layer. Then a mask is formed over the gate stack. The mask defines a gate electrode. We etch the gate stack and the endpoint detect layer using a multi-step etch comprising at least 3 steps. In a main etch step, the gate stack and the endpoint detect layer are etched using a first etch chemistry. Upon an endpoint detection signal generated by etching the gate stack, the first etch step is stopped. In an endpoint detect layer etch step, the gate stack layer and the endpoint detect layer are etched using a second etch chemistry. The endpoint etch step is stopped when an endpoint detect signal changes upon reaching the gate dielectric layer. The second etch chemistry has a higher selectivity from the gate dielectric layer to the gate stack layer and endpoint detect layer than the first etch chemistry. In an overetch step, using a third etch chemistry with a higher selectivity than the second etch chemistry, we etch the endpoint detect layer without damaging the gate dielectric layer.

Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system

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Singapore, Singapore

Tjin Tjin Tjoa