Texas Instruments Corporation

Tito Gelsomini

Giuliano Imondi

Pasqualino Fiorentino

A pair of like, semiconductor integrated circuit dies, such as DRAMS, have second level bonding pads formed over their active surfaces in mirror images of one another. The dies then become bonded to opposite sides of frame bonding pads of a lead frame to double the capacity of a normally encapsulated integrated circuit. The normal die bonding pads of the circuit dies are arranged identical to one another, and a patterned and etched second level of metal forms second level lands over the die bonding pads, the mirror image second level bonding pads and second level leads connecting corresponding second level lands to second level pads. A pair of 256K DRAMS can be connected either 256K.times.2 or 512K.times.1 by use of dummy second level pads for DATA-IN/OUT and ROW ADDRESSES STROBE connections.

Method of making a memory device by packaging two integrated circuit

A pair of like, semiconductor integrated circuit bars, such as DRAMS, have second level bonding pads formed over their active surfaces in mirror images of one another. The bars then become bonded to opposite sides of frame bonding pads of a lead frame to double the capacity of a normally encapsulated integrated circuit. The normal bar bonding pads of the circuit bars are arranged identical to one another, and a patterned and etched second level of metal forms second level lands over the bar bonding pads, the mirror image second level bonding pads and second level leads connecting corresponding second level lands to second level pads. A pair of 256K DRAMS can be connected either 256K.times.2 or 512K.times.1 by use of dummy second level pads for DATA-IN/OUT and ROW ADDRESS STROBE connection.

Semiconductor integrated circuit device having mirror image circuit bars

A dual port random access memory assembly having a custom tailored variable organization comprising a memory array or core (matrix) having, besides a pin for the supply voltage (VDD) connection and a pin for the ground voltage (GND) connection, a first and a second port, each port having two pins for supplying the control signals enabling the read and write operations, respectively; a set of pins for application of the address signals and a set of n data input/output (I/O) pins; wherein an organizer circuit is interposed between the n data input/output pins of the port which is to be organized or formatted and the memory array, which organizer circuit is driven by a number m of signals derived from a corresponding number m of data input/output pins of the output port and applied thereto through a corresponding number m of electronic switches and a corresponding number m of sharper circuits, so as to enable variable sets of bits to access to the memory through selective selts of input terminals and to convert up to a corresponding number m of data input/output pins of the port to be organized into a corresponding number m of additional address pins with respect to the latter port; the electronic switches being driven by a separate control signal.

Dual port random access memory having variably customized organization

A non-volatile memory device formed on a face of a semiconductor substrate which includes an array of electrically programmable read only memory cells, a Y address decoder coupled to said array and first and second sets of input/output lines coupled to said Y address decoder. Switch means isolates either the first or second set of input/output lines from the Y decoder. A programmable non-volatile memory element is coupled to programming ones of the input lines and is programmable into a programmed state from an unprogrammed state in response to a programming voltage applied to programming ones of the first set of input lines. A control circuit is coupled to the switch means and to the memory element for isolating the first or second set in response to an external signal applied to a selecting one of the first set of input/output lines and in response to the state of the non-volatile memory element.

Memory array with an array reorganizer

A device for changing the organization of an array of memory cells formed on a semiconductor ship using external control signals which includes a storage device for storing an external enable/disable command signal on the chip, a divider for dividing the array into blocks of memory cells in response to a stored enable command and a pass gate assembly for permitting access to selected ones of the blocks in response to corresponding toggle input signals when an enable command is stored.

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Rieti, Italy

Tito Gelsomini