Ati International Srl

Ati Technologies Ulc

Velocity Communication, Inc.

Tiruvur R Ramesh

Korbin S Van Dyke

John S Yates, Jr

Paul Henry Hohensee

David Reese

Sam Heidari

Behrooz Rezvani

Shalesh Thusoo

Avadhani Shridhar

Sanjay Mansingh

Raminder Singh Bajwa

Firooz Massoudi

Masoud Eskandari

Omprakash S Sarmaru

Sridhar Begur

A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code

A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

Method and apparatus for a X-DSL communication processor

A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

Floating point register stack management for CISC

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Union City, CA, United States of America

Tiruvur R Ramesh