Lam Research Corporation

Tiruchirapalli Arunagiri

William Thie

Yezdi N Dordi

Fritz C Redeker

John Boyd

Aleksander Owczarz

Alan M Schoepp

John P Parks

Arthur M Howald

John M Boyd

Todd Alan Balisky

Clint Thomas

Jacob Wylie

Shijian Li

Artur Kolics

Hyungsuk Alexander Yoon

Alex Yoon

Mikhail Korolik

Carl Woods

David J Hemker

Praveen Nalla

Benjamin W Mooring

Zhonghui Alex Wang

Johan Vertommen

A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.

Method and apparatus for wafer electroless plating

A cluster architecture and methods for processing a substrate are disclosed. The cluster architecture includes a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules. The lab-ambient controlled transfer module and the one or more wet substrate processing modules are configured to manage a first ambient environment. A vacuum transfer module that is coupled to the lab-ambient controlled transfer module and one or more plasma processing modules is also provided. The vacuum transfer module and the one or more plasma processing modules are configured to manage a second ambient environment. And, a controlled ambient transfer module that is coupled to the vacuum transfer module and one or more ambient processing modules is also included. The controlled ambient transfer module and the one or more ambient processing modules are configured to manage a third ambient environment. The cluster architecture therefore enables controlled processing of the substrate in either the first, second or third ambient environments, as well as during associated transitions.

Controlled ambient system for interface engineering

A chemical fluid handling system is defined to supply a number of chemicals to a number of fluid inputs of a mixing manifold. The chemical fluid handling system includes a number of fluid recirculation loops for separately pre-conditioning and controlling the supply of each of the number of chemicals. Each of the fluid recirculation loops is defined to degas, heat, and filter a particular one of the number of chemical components. The mixing manifold is defined to mix the number of chemicals to form the electroless plating solution. The mixing manifold includes a fluid output connected to a supply line. The supply line is connected to supply the electroless plating solution to a fluid bowl within an electroless plating chamber.

Fluid handling system for wafer electroless plating and associated methods

One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.

Post-deposition cleaning methods for substrates with cap layers

The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically copper-to-cobalt-alloy interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a thin layer of a cobalt-alloy material on a copper surface of a copper interconnect of the substrate in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes removing contaminants and metal oxides from the substrate surface in the integrated system, and reconditioning the substrate surface using a reducing environment after removing contaminants and metal oxides in the integrated system. The method also includes selectively depositing the thin layer of cobalt-alloy material on the copper surface of the copper interconnect in the integrated system after reconditioning the substrate surface. An exemplary system to practice the exemplary method described above is also provided.

Processes and systems for engineering a copper surface for selective metal deposition

The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve silicon-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce a silicon-to-metal interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a layer of a metal on a silicon or polysilicon surface of the substrate to form a metal silicide in an integrated system is provided. The method includes removing organic contaminants from the substrate surface in the integrated system, and reducing the silicon or polysilicon surface in the integrated system after removing organic contaminants to convert silicon oxide on the silicon or polysilicon surface to silicon, wherein after reducing the silicon or polysilicon surface, the substrate is transferred and processed in controlled environment to prevent the formation of silicon oxide, the silicon or polysilicon surface is reduced to increase the selectivity of the metal on the silicon surface. The method further includes selectively depositing the layer of the metal on the silicon or polysilicon surface of substrate in the integrated system after reducing the silicon or polysilicon surface. An exemplary system to practice the exemplary method described above is also provided.

Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide

Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after plating processes are provided. In particular, solutions are provided which are free of oxidizing agents and include a non-metal pH adjusting agent in sufficient concentration such that the solution has a pH between approximately 7.5 and approximately 12.0. In some cases, a solution may include a chelating agent. In addition or alternatively, a solution may include at least two different types of complexing agents each offering a single point of attachment for binding metal ions via respectively different functional groups. In any case, at least one of the complexing agents or the chelating agent includes a non-amine or non-imine functional group. An embodiment of a method for processing a substrate includes plating a metal layer upon the substrate and subsequently exposing the substrate to a solution comprising the aforementioned make-up.

Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after a plating process

Post-deposition cleaning methods and formulations for substrates with cap layers

A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

Wafer electroless plating system and associated methods

The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect. The method also includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method further includes depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system. An exemplary system to practice the exemplary method described above is also provided.

Processes and systems for engineering a barrier surface for copper deposition

This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

Methods and systems for barrier layer surface passivation

An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

Interconnect structure and method of manufacturing a damascene structure

Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.

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Fremont, CA, United States of America

Tiruchirapalli Arunagiri