Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

Tirdad Sowlati

Sifen Luo

Vickram R Vathulya

Kerry Burger

Chris Joly

A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.

Interdigitated multilayer capacitor structure for deep sub-micron CMOS

A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180 &deg;. The dc bias circuit includes a dynamic bias boosting circuit for increasing the dc bias current provided to the amplifying transistor by the dc bias current in direct proportion to an increase in the input signal provided to the power amplifier. An input to the dc bias circuit is coupled to a stage of the power amplifier circuit by a capacitor. The bias boosting circuit permits the power amplifier circuits to operate in Class B or Class AB with improved linearity, improved efficiency and reduced idle current.

Capacitor coupled dynamic bias boosting circuit for a power amplifier

A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of electrically conductive parallel lines arranged in vertical rows, and at least one via connecting the first and second levels of lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. A dielectric material is disposed between the vertical plates of the array. The vertical array of capacitor plates are electrically connected to the alternating source and drain regions of the transistor which form opposing nodes of the capacitor and electrically interdigitate the vertical array of capacitor plates.

Combined transistor-capacitor structure in deep sub-micron CMOS for power amplifiers

A shorting element, preferably a resonant inductor-capacitor circuit, is inserted in parallel with a sense transistor, which itself is in parallel with a power transistor. The use of the shorting element in combination with the sense transistor, provides a technique to have a monotonic power detection. The shorting element eliminates extraneous currents caused by inherent collector-base and collector-substrate diodes of sense transistor, and also eliminates the extraneous collector voltage swing of the sense transistor caused by mutual coupling between inductors connected to the power and sense transistors.

Power measurement circuit including harmonic filter

A bias circuit having a relatively long time constant improves the linearity of a radio frequency power amplifier of a spread spectrum mobile telephone by causing a power transistor of the amplifier to operate in class A or AB mode. The power amplifier thus derives an output signal that is a substantial replica of the spread spectrum input signal for all amplitudes of the input signal. The bias circuit has transistors connected in a feedback circuit which tends to oscillate to affect the amplifier operation. A low pass filter connected to the transistors suppresses the tendency. An interstage high pass matching circuit between a linear amplifier that drives the power amplifier includes a series capacitor and an inductor connected between an output terminal of the linear amplifier and a DC power supply terminal.

Radio frequency power amplifier for cellular telephones

A high-frequency integrated transistor module includes a bipolar transistor having at least one emitter finger, which is internally connected in series with a resistor to provide a DC current path for the circuit, and is internally connected in series with a capacitor to provide an RF current path for the module separate from the DC current path. The capacitor may be coupled to an RF ground connection, and the value of the capacitor may be selected to resonate with the value of the RF ground connection inductance in order to provide gain enhancement at a selected operating frequency range. In order to provide gain enhancement over a broader frequency bandwidth, two or more emitter fingers can be connected in series with respective capacitors of different values in order to provide at least two RF current paths having different resonant frequencies.

High-frequency integrated transistor module

A capacitor structure, especially for use in deep sub-micron CMOS, having an array of electrically conductive pillars which form the plates of the capacitor. Each of the pillars is formed by electrically conductive lines segments from at least two different conductor levels electrically connected by an electrically conductive via. Dielectric material is disposed between the two conductor levels and the pillars of the array. The pillars are electrically connected to opposing nodes in an alternating manner so that the pillars are electrically interdigitated.

Multilayer pillar array capacitor structure for deep sub-micron CMOS

A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifying transistor to obtain a conduction angle of less than about 180&deg;. The dc bias circuit includes a dynamic biasing circuit for decreasing the dc bias signal provided to the amplifying transistor as the input signal to the power amplifier circuit increases. This configuration permits the amplifier circuit to operate as a linearized Class C amplifier, having a substantially linear input-output relationship similar to that of a Class B amplifier, but with increased operating efficiency.

Linearized class C amplifier with dynamic biasing

A method for increasing the maximum useable supply voltage in an amplifier circuit is presented. A self-biased cascode amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a DC voltage source terminal and a common terminal. An RF input signal terminal is coupled to a gate electrode of the first MOSFET, and the gate of the second MOSFET is connected between a resistor and a capacitor connected in series between the drain of the second MOSFET and the source of the first MOSFET. In preferred embodiments a unidirectionally-conducting boosting sub-circuit is coupled between a drain electrode and the gate electrode of the second MOSFET, which may comprise a diode-resistive sub-circuit, or a third MOSFET connected across a resistive voltage divider. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET. These configuration permits the first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and increased output power, without the necessity of complex biasing voltages.

Self-biased cascode RF power amplifier in sub-micron technical field

A bootstrapped dual-gate Class E amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a dc voltage source terminal and a common terminal. An rf input signal terminal is coupled to a gate electrode of the first MOSFET and a dc control voltage terminal is coupled to a gate electrode of the second MOSFET, with a unidirectionally-conducting element such as a diode-connected MOSFET being coupled between a drain electrode and the gate electrode of the second MOSFET. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET. This circuit configuration permits the first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and resulting in a substantially increased maximum output power capability for a given load value.

Bootstrapped dual-gate class E amplifier circuit

A cascode bootstrapped analog power amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a dc voltage source terminal and a common terminal. An rf input signal terminal is coupled to a gate electrode of the first MOSFET and a dc control voltage terminal is coupled to a gate electrode of the second MOSFET, with a unidirectionally-conducting element such as a diode-connected MOSFET being coupled between a drain electrode and the gate electrode of the second MOSFET. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET. This circuit configuration, permits he first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and resulting in a substantially increased maximum output power capability for a given load value.

Cascode bootstrapped analog power amplifier circuit

A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180&deg;. The dc bias circuit includes a self-bias boosting circuit for initially decreasing and then increasing the dc bias voltage provided to a control terminal of the amplifying transistor by the dc bias circuit as the input signal provided to the power amplifier increases. The self-bias boosting circuit is extremely simple and compact in design, and permits the power amplifier circuits to operate in Class B or Class AB with improved power output characteristics.

Self-boosting circuit for a power amplifier

A high-frequency amplifier circuit includes an amplifying transistor and a bias circuit directly connected to said amplifying transistor. The bias circuit includes a bias transistor having a control terminal and an inductor coupled to the control terminal, and the bias transistor also has an output terminal directly connected to the amplifying transistor. A resistor is connected in series with the inductor, and the series-connected components are connected in the circuit between the control terminal and a power supply terminal. By providing an inductor in the amplifier in this manner, loading effects on the amplifying transistor at high frequencies is substantially reduced.

High-frequency amplifier circuit having a directly-connected bias circuit

A power amplifier circuit for amplifying an input signal includes an amplifying transistor and a power detection circuit. The power detection circuit includes a circuit for generating a signal which is directly proportional to the power level in the amplifying transistor. This may-be accomplished by generating a voltage proportional to the square of a current in the amplifying transistor and then averaging that voltage. In this manner, a more accurate indication of the power level in the amplifying transistor is obtained.

Accurate power detection circuit for use in a power amplifier

A high-frequency amplifier circuit includes an amplifying transistor and a driver transistor, with the amplifying transistor being connected in either a common emitter or a common source configuration and the driver transistor being connected in a corresponding common collector or a common drain configuration, depending upon whether bipolar or field effect transistors are used. A current-mirror bias circuit is coupled between an input terminal and an output terminal of the driver transistor, with a resistor being provided for coupling the current mirror to the input terminal of the driver transistor. The resistor, which typically has a value of between about 20 and 100 ohms, provides a negative impedance cancellation effect while minimizing power consumption at low bias levels.

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Ossining, NY, United States of America

Tirdad Sowlati