Cypress Semiconductor Corporation

Spansion Llc.

Tio Wei Neo

Shivananda Shetty

Chun Chen

Yoram Betser

Pawan Kishore Singh

Giovanni Mazzeo

Kuo-Tung Chang

Kuo Tung Chang

Richard M Fastow

Mark W Randolph

Yi He

Zhizheng Liu

James Minsu Pak

Gulzar Ahmed Kathawala

Harry Kuo

Cindy Sun

Phuong Banh

Loi La

Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Suppression of program disturb with bit line and select gate voltage regulation

Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.

Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

Multi-pass soft programming

Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.

Adaptively programming or erasing flash memory blocks

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Fremont, CA, United States of America

Tio Wei Neo