Hkc Corporation Limited

Tingting Shen

Baohong Kang

ZhiWei Li

Yunyang Liu

Guangchen Zhang

Li Lv

Haijiang Yuan

Yuchun Xu

Ying Chen

Rongrong Li

Haoxuan Zheng

Jie Wang

Disclosed are a pixel circuit, a method for controlling a pixel and a display panel. The pixel circuit includes a first thin film transistor, a controlled end of the first thin film transistor is connected to the scan line, and an input end of the first thin film transistor is connected to the data line; and a first selection circuit, an input end of the first selection circuit is connected to an output end of the first thin film transistor, the first output end of the first selection circuit is connected to the first pixel electrode, and a second output end of the first selection circuit is connected to the second pixel electrode; the first thin film transistor is configured to sequentially write a data signal transmitted on the data line into the first pixel and the second pixel through the first selection circuit.

Pixel circuit, method for controlling pixel and display device

A control circuit of a display panel, and a display device. The control circuit of a display panel is configured to receive a first clock signal, a first level signal and a second level signal, phase-shift the first clock signal to obtain a second clock signal according to the first level signal and the second level signal and output the second clock signal to a gate drive circuit. The clock signal is phase-shifted to reduce the load of a single clock signal and minimize the number of clock generators in the display panel, thereby reducing the production cost of the display panel.

Control circuit of display panel and display device

A gate-on-array (GOA) drive circuit. The GOA drive circuit includes multi-stage cascaded GOA circuits, and each stage of the GOA circuits includes a GOA circuit unit and a signal split circuit that are connected to each other. The signal split circuit is in connection with two adjacent scanning lines. The GOA circuit unit operates in the same mode as the existing GOA circuit unit. The output line scan signal serves as the input signal of the GOA circuit unit at the post-stage as well as the reset signal of the GOA circuit unit at the fore-stage. Moreover, the signal split circuit splits the line scan signal of the current stage into the first sub-line scan signal and the second sub-line scan signal and output the same, thereby realizing the scanning and driving of the two rows of pixel units.

Gate-on-array drive circuit, display panel, and display device

The irregularly-shaped display panel comprises a plurality of pixel units arranged in an array and a shielding layer. some of the pixel units are shielded by the shielding layer to form irregularly-shaped pixel units, and each of the irregularly-shaped pixel unit at least comprises a first irregularly-shaped pixel unit; in the first irregularly-shaped pixel unit, the areas of opening regions of at least two sub-pixels shielded by the shielding layer are different, and the sub-pixel having a larger area of an opening region shielded by the shielding layer has a greater pixel pressure difference.

Irregularly-shaped display panel and display device

A display module includes a display unit for image displaying and provided with a light-emitting side, the display module further includes an outer encapsulation layer provided on the light-emitting side of the display unit, and is provided to cover at least an edge of the display unit; the outer encapsulation layer is made of self-healing glass material; and a traction assembly including a first connection piece and a second connection piece with magnetic adsorption, the display unit is provided with a splicing portion for splicing the display modules, the first connection piece and the second connection piece are provided in the splicing portion; the first connection piece and the second connection piece are used for providing the outer encapsulation layers of the two spliced display modules with required fusion force when the display modules are spliced.

Display module and spliced display device

A drive circuit for a display panel, including a generation module, an output module and a switch control module. The output module is in electric connection with the generation module and the switch control module. The output module is configured to output a generation signal to a gate driver according to a switch control signal. The output module is further configured to output a first clock signal and a second clock signal to the gate driver according to the switch control signal. The refresh rate of the display panel can be changed in real time, and the power consumption of the display panel having high refresh rate is reduced; meanwhile, the signals outputted by the output module can be continuous, so as to improve the display effect of the display panel and prolong the service life of the display panel.

Drive circuit for display panel and display device

A pixel drive circuit, which includes: a first thin film transistor, a first unidirectional conduction switch, a second thin film transistor, a second unidirectional conduction switch, and a pixel capacitor; and the first thin film transistor includes: a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode being connected with a n-th scan line, the first source electrode being connected with a m-th scan line, and the first drain electrode being connected with the pixel capacitor, and the n and m are positive integers; the second thin film transistor includes: a second gate electrode, a second source electrode, and a second drain electrode; the second gate electrode being connected with a (n−1)-th scan line, the second source electrode being connected with the pixel capacitor, and the second drain electrode being grounded.

Pixel drive circuit and display panel

A display circuit of a special-shaped screen and a display device. The display circuit includes multiple pixel circuits arranged in a special-shaped region of the special-shaped screen in a manner of a non-rectangular array; pixel circuits located at both ends of each row of the plurality of pixel circuits being edge pixel circuits, one of two adjacent edge pixel circuits being connected to a Nlevel gate signal line, the other one of the two adjacent edge pixel circuits being connected to a (N+1)level gate signal line, and N is a natural number greater than 0; a voltage-dividing circuit connected to each of the two adjacent edge pixel circuits, to enable the two adjacent edge pixel circuits to have equal storage voltages, a control end of the voltage-dividing circuit being connected to a (N+M)level gate signal line, and M being a natural number greater than 2.

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Shenzhen, China

Tingting Shen