Taiwan Semiconductor Manufacturing Comp. Ltd.

Tingting Lu

Mu-Jen Huang

Feng Zhu

Weiyang Jiang

Lin Sun

Zhi Zhong Hu

In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.

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Songjiang District, China

Tingting Lu