Shanghai Avic Opto Electronics Co., Ltd.

Shanghai Tianma Micro-Electronics Co., Ltd.

Tianma Micro-Electronics Co., Ltd.

Shanghai Tianma Am-Oled Co., Ltd.

Chengdu Tianma Micro-Electronics Co., Ltd.

Tingting Cui

Kerui Xi

Feng Qin

Xuhui Peng

Xiaohe Li

Jine Liu

Zhaokeng Cao

Baiquan Lin

Dandan Qin

Jie Zhang

Zhenyu Jia

Junting Ouyang

Zhonglan Cai

Yuan Yuan Ding

Xiangjian Kong

Qinyi Duan

Boquan Lin

Jiubin Zhou

Guicai Wang

Yajie Wang

Xingyao Zhou

Chen Xiao Wang

Ruiyuan Zhou

Juan Zhu

Qiongqin Mao

Yuantao Wu

Linzhi Wang

Zuocai Yang

Ping Su

Zuzhao Xu

Yumin Han

The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire.

Package structure, packaging method, camera module, and electronic equipment

A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.

Semiconductor package having a semiconductor element and a wiring structure

Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.

Chip package method and chip package structure

A panel includes a substrate, an array layer and an electrode array layer. The array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer. The substrate includes drive units arranged in an array, scan line groups, data lines extending in a second direction; and common signal lines extending in the second direction. The scan line group includes first scan lines and second scan lines, extending in a first direction. The first direction is perpendicular with the second direction. The electrode array layer includes drive electrodes arranged in an array; the drive electrodes correspond to the drive units; and the drive unit includes a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor.

Panel and drive method thereof

Provided are an antenna, a phase shifter, and a communication device. The antenna includes a first metal electrode, a second metal electrode, and a photo-sensitive layer. The first metal electrode and the second metal electrode are respectively located on two opposite sides of the photo-sensitive layer. The first metal electrode includes multiple transmission electrodes. The multiple transmission electrodes are configured to transmit electrical signals. The photo-sensitive layer includes at least one photo-sensitive unit and the at least one photo-sensitive unit overlaps the transmission electrodes. The antenna provides more possibilities for large-scale commercialization.

Antenna, phase shifter, and communication device

A phase shifter, a fabrication method thereof, and an antenna are provided. The phase shifter includes a first substrate, a second substrate, a ground electrode disposed on a side of the first substrate facing towards the second substrate, a transmission electrode disposed on a side of the second substrate facing towards the first substrate, and liquid crystals filled between the first substrate and the second substrate. In a direction perpendicular to a plane of the second substrate, the transmission electrode overlaps with the ground electrode. The ground electrode is provided with a detection hollow part, and in the direction perpendicular to the plane of the second substrate, at least a part of the detection hollow part does not overlap with the transmission electrode.

Phase shifter, fabrication method thereof, and antenna

Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.

Semiconductor package and method for fabricating the semiconductor package

Disclosed antenna unit includes first substrate and second substrate opposite to each other, phase shifting units and driver circuit. Region facing the first substrate and the second substrate form phase shifting region. In first direction, the first substrate formed with first step region, and used for connecting radio-frequency signal terminal; in second direction, the second substrate formed with second step region, and included angle between the first direction and the second direction greater than or equal to 0&#xb0; and smaller than 180&#xb0;. At least part of the first step region does not overlap at least part of the second step region. Phase shifting units used for radiating radio-frequency signal and distributed in phase shifting region, each phase shifting unit. At least part of the driver circuit disposed in the second step region and the driver circuit electrically connected to each phase shifting unit to adjust radio-frequency signal.

Antenna unit, antenna apparatus and electronic device

Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Packaging method of panel-level chip device

A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

Semiconductor package having semiconductor element with pins and formation method thereof

A phase shifter and a manufacturing method thereof and an antenna and a manufacturing method thereof are provided. The phase shifter includes: first and second substrates opposite to each other; a first electrode provided on the first substrate and configured to receive a ground signal; a second electrode provided on a side of the second substrate facing towards the first substrate; liquid crystals encapsulated between the first substrate and the second substrate and driven by the first electrode and the second electrode to rotate; and a support structure provided between the first substrate and the second substrate and including a first spacer. The first spacer is located on a side of the second electrode facing away from the second substrate, and an orthographic projection of the first spacer on the second substrate is within an orthographic projection of the second electrode on the second substrate.

Phase shifter and manufacturing method thereof, antenna and manufacturing method thereof

A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal. The step-up unit includes a first module, a second module and a first capacitor. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor at a first time period which generates a voltage difference between two electrodes of the first capacitor, and to transmit the signal of the fourth signal input terminal to the second electrode of the first capacitor at a second time period which further increases a signal of the first electrode of the first capacitor.

Drive circuit and drive method thereof, and panel and drive method thereof

Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes exposes one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.

Semiconductor package including workpiece and method for fabricating the semiconductor package

Fingerprint recognition circuit, fingerprint recognition structure, fingerprint recognition device, display panel, and display device are provided. The circuit includes: a fingerprint recognition driving transistor; a first capacitor; a driving signal input terminal; and a sensing signal output terminal. The first capacitor has a terminal electrically connected to a gate of the fingerprint recognition driving transistor and another terminal electrically connected to a ground. The driving signal input terminal is electrically connected to an input terminal of the fingerprint recognition driving transistor. An output terminal of the fingerprint recognition driving transistor is electrically connected to the sensing signal output terminal.

Circuit, structure, and device for fingerprint recognition, display panel, and display device

Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.

Growing community of inventors

Shanghai, China

Tingting Cui