Integrated Device Technology, Inc.

Netlogic Microsystems, Inc

Tingjun Wen

Tadeusz Kwasniewski

David Walter Carr

An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n&#x2212;1, . . . , 0]) and a second n-bit operand (e.g., B[n&#x2212;1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: 'n' is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.

Packet processors having comparators therein that determine non-strict inequalities between applied operands

A search engine device includes a lookup circuit, such as a content addressable memory (CAM) array. This lookup circuit is configured to generate multiple active match signals in response to detecting multiple matches between a search operand applied to said lookup circuit and multiple entries therein, during a search operation. A priority sequencer circuit is also provided. This priority sequencer circuit, which is electrically coupled to outputs of the lookup circuit, is configured to sequentially encode each of the multiple active match signals according to priority.

Integrated circuit search engine devices having priority sequencer circuits therein that sequentially encode multiple match signals

Content addressable memory (CAM) devices have CAM cells therein that are electrically coupled to a NAND-type compare circuit. This NAND-type compare circuit is responsive to a first operand (K) containing true and complementary bits of an applied search key and a second operand (D) containing true and complementary bits of a stored search word. The NAND-type compare circuit includes a first string of transistors connected end-to-end in series from a first terminal to a second terminal and a second string of transistors connected end-to-end in series from the first terminal to the second terminal. This first string of transistors has gate terminals responsive to the first operand and the second string of transistors has gate terminals responsive to the second operand.

Content addressable memory (CAM) devices having NAND-type compare circuits

A multi-functional match cell is responsive to first and second n-bit operands and configured so that the match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit operand is masked and as an n-bit NAND-type CAM cell when the first n-bit operand is masked, where 'n' is a positive integer greater than one.

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Kanata, Canada

Tingjun Wen