Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

East Sun Rising Enterprise Corporation

Ting-Yu Chen

Li-Chun Tien

Jung-Chan Yang

Chi-Yu Lu

Guo-Huei Wu

Lee-Chung Lu

Ta-Pen Guo

Chung-Cheng Wu

Min Cao

Chen-Yuan Kao

Hsiang-Jen Tseng

Yung-Chin Hou

Shyue-Shyh Lin

Shu-Hui Sung

Ali Keshavarzi

Wei-Hsin Tsai

Yu-Lun Wan

Bor-Yueh Liu

A testing circuit is provided. The testing circuit includes a clock cone, a series of shift register chains, and a control circuit. The clock cone is divided into a plurality of fan-out partitions operated in the same clock domain. The shift register chains are configured to shift out one-hot signals on demand and each shift register chain includes multiple registers with the same amount as fan-out partitions. The control circuit receives the one-hot signals from the shift register chains and enables the divided fan-out partitions therefore.

Testing circuit

A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.

Integrated circuit

An integrated circuit is disclosure. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in the first layer parallel to the first pair of power rails, a first set of active areas. The integrated circuit further includes a first gate arranged along the second direction, between the first pair of power rails, and crossing the first set of active areas in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and a second gate and a third gate, in which the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor which is coupled to the control terminal of the third transistor.

A semiconductor device includes a first group of semiconductor fins arranged at a first fin-to-fin spacing and a second group of semiconductor fins arranged at a second fin-to-fin spacing. The first and second groups of semiconductor fins are separated by a fin-free region larger than the first and second fin-to-fin spacings. The semiconductor device further includes a gate structure extending across the first and second group of semiconductor fins, a Vdd line and a Vss line extending across the gate structure. The first and second groups of semiconductor fins are between the Vdd line and the Vss line from a top view, and an overlapping area between the Vdd line and the first group of semiconductor fins is different from an overlapping area between the Vss line and the second group of semiconductor fins from the top view.

Integrated circuit layout with asymmetric metal lines

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Integrated circuits and manufacturing methods thereof

A method of manufacturing a solar cell, including providing a patterned silicon wafer having a covered area and an uncovered area, and forming at least one electrode layer in the uncovered area in a low-temperature process.

Method for manufacturing a solar cell

Growing community of inventors

Hsinchu, Taiwan

Ting-Yu Chen