Advanced Micro Devices Corporation

Texas Instruments Corporation

Ting Yiu Tsui

Robert Kraft

Yowjuang William Liu

Sunil Narayan Shabde

Andrew McKerrow

Satyavolu Srinivas Papa Rao

Haowen Bu

Ping Jiang

Ercan Adem

David Gerald Farber

Young-Chang Joo

Jeannette Michelle Jacques

Sunil D Mehta

Jiong-Ping Lu

Qi-Zhong Hong

Deepak Arabagatte Ramappa

Mona M Eissa

Xiao-yu Li

Stephen Keetai Park

Changming Jin

Jeremy Isaac Martin

Reading G Maley

Tz-Cheng Chiu

Christian Zistl

Kenneth Joseph Newton

Hyesook Hong

Craig Henry Huffman

Robert H Tu

William Wesley Dostalik

Christopher Lyle Borst

David Permana

Yuji Richard Kuan

The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (). A strain inducing liner is formed over the semiconductor device (). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region ().

Systems and methods that selectively modify liner induced stress

The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Energy beam treatment to improve packaging reliability

The present invention provides an insulating layerfor an integrated circuitcomprising a porous silicon-based dielectric layerlocated over a substrate. The insulating layer comprises a densified layercomprising an uppermost portionof the porous silicon-based dielectric layer.

Method to increase mechanical fracture robustness of porous low k dielectric materials

A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Methods to facilitate etch uniformity and selectivity

An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step), modifying a top surface of the spin-on glass material to form a SiOlayer (step), applying a vapor prime (step), forming a photoresist layer over the spin-on-glass material (step), patterning the photoresist layer (step), and then etching the semiconductor wafer (step). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step), modifying a top surface of the spin-on glass material to form a SiOlayer (step), applying a vapor prime (step), forming a photoresist layer over said spin-on-glass material (step), patterning the photoresist layer (step), and etching trench spaces (step).

Plasma treatment for silicon-based dielectrics

Methods () are presented for protecting copper structures () from corrosion in the fabrication of semiconductor devices (), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer () is formed on an exposed surface () of a copper structure () prior to performance of metrology operations (), so as to inhibit corrosion of the copper structure (). All or a portion of the corrosion protection layer () is then removed () in forming an opening in an overlying dielectric () in a subsequent interconnect layer.

Post-polish treatment for inhibiting copper corrosion

One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Method of passivating and/or removing contaminants on a low-k dielectric/copper surface

Disclosed is a system for fabricating a semiconductor device (). An interconnect structure () is formed on the semiconductor device () and a cap () is deposited over the interconnect structure (). The interconnect structure () is annealed with the overlying cap () in place. The cap () is then removed after the interconnect structure () is annealed.

System for improving thermal stability of copper damascene structure

A method is provided, the method comprising forming a dielectric layer above a structure layer, forming a hard mask layer above the dielectric layer, and forming at least one trench opening and at least one upper portion of a first via opening in the dielectric layer through the hard mask layer. The method also comprises forming a low viscosity photoresist layer above the at least one trench opening and the at least one upper portion of the first via opening in the dielectric layer.

Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist

The present invention provides, in one embodiment, process of treating a target semiconductor surface. The process includes exposing a test surface to a plasma protocol ( ), and measuring chemical changes in discrete locations of the test surface ( ). The process further includes preparing a target surface by exposing the target surface to the plasma protocol ( ) when a uniformity of the chemical changes are within a performance criterion of the plasma protocol ( ). Other embodiments advantageously incorporate this process into methods for making semiconductor devices and integrated circuits.

Method for fabricating semiconductor devices that uses efficient plasmas

An embodiment of the invention is a metal layer of a back-end module where the height of the interconnects is greater than the height of the dielectric regions . Another embodiment of the invention is a method of fabricating a semiconductor wafer where the height of the interconnects is greater than the height of the dielectric regions

Etch back of interconnect dielectrics

A method is provided, the method comprising programming a silicide fuse by passing a current through the silicide fuse while substantially simultaneously irradiating the silicide fuse with a laser.

Laser-assisted silicide fuse programming

A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Semiconductor device having a low dielectric constant material

A method is provided, the method comprising forming a first dielectric layer above a structure layer, the first dielectric layer having an upper portion. The method also comprises grading the upper portion of the first dielectric layer using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N O) and molecular nitrogen (O ).

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Dallas, TX, United States of America

Ting Yiu Tsui