Realtek Semiconductor Inc.

Ting-Ying Wu

Ruey-Beei Wu

Wen-Shan Wang

Chin-Yuan Lo

Shih-Hung Wang

Chih-Wei Chang

Gerchih Chou

Chun-Ming Huang

Nan-Chin Chuang

Ming-Chung Huang

Hsin-Hui Lo

Shu-Min Wu

Chien-Hsiang Huang

Han-Yun Tsai

Hsin-Chan Hsieh

Cheng-Lin Wu

Po-Chun Chen

Tse-Yi Hsieh

An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Electronic device test method and test device

A method for performing memory calibration and an associated System on Chip (SoC) Integrated Circuit (IC) are provided. The method may include: in a power-up and initialization phase, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory; in an impedance-calibration-related phase, triggering the memory to perform impedance calibration regarding a set of data pins; in at least one subsequent phase, during performing any calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and according to whether the data access test is successful, selectively stopping the any calibration operation.

Method for performing memory calibration, associated system on chip integrated circuit and non-transitory computer-readable medium

A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Power line structure

An electromagnetic band gap structure apparatus includes a first conducting layer having at least one first slot. Each of the at least one slot is arranged with a planar conductor unit, and the each planar conductor unit is coupled to a first via. The electromagnetic band gap structure apparatus further includes a second conducting layer in parallel with the first conducting layer. The second conducting layer has a second slot. The second slot is arranged with at least one planar transmission line unit. The each of the at least one planar transmission line unit is coupled to the first conducting layer through a second via, and the each first via is coupled to the second conducting layer.

Electromagnetic band gap structure apparatus

An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

Electronic package structure with a core ground wire and chip thereof

A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.

Memory device including noise-suppressing mechanism

A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.

Ball grid array formed on printed circuit board

Disclosed is a two-capacitor-based filter design method comprising: determining a frequency fand a fractional bandwidth ratio FBW; selecting a first and a second capacitors according to fand FBW, in which a resonant frequency fof the first capacitor is equal to f&#xd7;(1&#x2212;N&#xd7;FBW), a resonant frequency fof the second capacitor is equal to f&#xd7;(1+M&#xd7;FBW), and each of N and M is a positive number less than one; and determining a length of a first transmission line according to fand a signal speed, and determining a length of a second transmission line according to fand the signal speed. The first capacitor is coupled between a center of the first transmission line and ground, the second capacitor is coupled between a center of the second transmission line and ground, and the first and second transmission lines are connected in series.

Two-capacitor-based filter design method and two-capacitor-based filter

An impedance correction device and a method thereof are provided. A step generator is used to generate a step signal and send to a circuit under test. A reflected signal returned back from the circuit under test is used as a measurement signal; and the measurement signal can be measured to obtain a characteristic impedance value. When the measurement signal is greater than the initially measured step signal, an impedance value of a correction resistor is increased; when the measurement signal is smaller than the initially measured step signal, the impedance value of the correction resistor is reduced. Through adjustment of the correction impedance value, impedance matching between the correction impedance value and the characteristic impedance value is achieved.

Growing community of inventors

Hsinchu County, Taiwan

Ting-Ying Wu