Rambus Inc.

Norel Systems Limited

Silicon Image Gmbh

Ting Wu

Kun-Yung Chang

Chintan S Thakkar

Carl William Werner

Hae-Chang Lee

Farshid Aryanfar

Yuanlong Wang

Masoud Koochakzadeh

Wei Zhao

Kambiz Kaviani

Jie Shen

Omid Rajaee

Hui Wang

Jason Chia-Jen Wei

Miao Chen

Kun-Yang (Ken) Chang

An intelligent mobile power supply and a method for USB data communication therewith. The intelligent mobile power supply includes a battery, a charging control module, a discharging control module, a first USB interface and a second USB interface. In the single charging mode, a charged device receives a discharge of the intelligent mobile power supply through the discharging control module, but the intelligent mobile power supply does not perform USB data communication with the charged device. While in the charging and communication mode, the charged device receives the discharge of the intelligent mobile power supply through the discharging control module and can perform USB data communication with the intelligent mobile power supply through the first USB interface simultaneously. The second USB interface is connected with the charging control module, and the second USB interface can be connected with a power adapter or a PC host to charge the battery.

Intelligent mobile power supply and method for USB data communication therewith

A charging detection and control apparatus for an Apple device, including: a charging input interface, a detection apparatus, a control apparatus and a charging output interface. An input terminal of the detection apparatus is connected to a charging source terminal via the charging input interface, an output terminal of the detection apparatus is connected to an input terminal of the control apparatus, an output terminal of the control apparatus is connected to the Apple device via the charging output interface, the detection apparatus detects a capacity for charging current of the charging source terminal inserted into the charging input interface, and outputs a detection result to the control apparatus, the control apparatus converts the received detection result into a charging parameter complying with Apple standards, and sends the charging parameter to the Apple device via the charging output interface.

Charging detection and control apparatus

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Apparatus and method for un-delayed decision feedback with sample and hold at selected timing

Partial response equalizer and related method

A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

Signal distribution networks and related methods

A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.

Partial response decision feedback equalizer with distributed control

A linear equalizer (LEQ) includes a first transconductance device coupled to an input node of the LEQ and a second transconductance device AC coupled to the input node of the LEQ to increase a gain of the LEQ for data signals above a predetermined frequency. The first transconductance device and the second transconductance device are of complimentary types. A bimodal LEQ includes inputs to control operation of the bimodal LEQ in a current mode or a voltage mode. The bimodal LEQ includes first and second transconductance devices. One of the first and second transconductance devices is AC coupled to an input node to increase the gain for data signals above a predetermined frequency.

Linear equalizer

Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal.

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Tianjin, China

Ting Wu