Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-shan Institute of Science and Technology, Armaments Bureau, M.n.d

Chung-shan Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense

Ting-Wei Chiang

Hui-Zhong Zhuang

Li-Chun Tien

Jung-Chan Yang

Chung-Te Lin

Pin-Dai Sue

Lee-Chung Lu

Chi-Yu Lu

Hsiang-Jen Tseng

Shang-Chih Hsieh

Ting Yu Chen

Shun Li Chen

Tung-Heng Hsieh

Sheng-Hsiung Wang

Cheng-I Huang

Wei-Yu Chen

Chun-Fu Chen

Ya-Chi Chou

Po-Hsiang Huang

Yu-Jung Chang

Pochun Wang

Jerry Chang-Jui Kao

Fong-yuan Chang

Sheng-Hsiung Chen

XinYong Wang

Ru-Gun Liu

Chih-Ming Lai

Shih-Ming Chang

Stefan Rusu

Yu-Xuan Huang

Yi-Hsiung Lin

Guo-Huei Wu

Chi-Lin Liu

Jung-Hsuan Chen

Meng-Hung Shen

Shao-Lun Chien

Mao-Wei Chiu

Che Min Huang

Kuo-Nan Yang

Jerry Chang Jui Kao

Chun-Chen Chen

Lipen Yuan

Jyun-Hao Chang

You-Cheng Xiao

Jian-Sing Li

Ni-Wan Fan

Ru-Yu Wang

I-Lun Tseng

Sang Hoo Dhong

Yu-Ti Su

Shih-Chi Fu

Wei-Hsiang Ma

Jiun-Jia Huang

Yi-Yuh Hwang

Shun-Li Chen

Sheng-Fang Cheng

Chin-Der Hwang

Chih-Ming Liao

Wen-Cheng Huang

Hsueh-Chih Chou

Chia Hao Tu

Jhih-Siang Hu

Jiann-Tyng Tzeng

Chih-Liang Chen

Ta-Pen Guo

Yi-Hsun Chiu

Ming-Hsiang Song

Fong-Yuan Chang

Min-Hsiung Chiang

Tzu-Ying Lin

Zhe-Wei Jiang

Po-Chia Lai

Shang-Wei Fang

Kuang-Ching Chang

Ruei-Wun Sun

Shin-I Ma

Mau-Ran Wang

Hsiang Jen Tseng

Hung-Jung Tseng

Chun-Hao Chen

Tzung-Yo Hung

Chih-Wei Chang

Xiangdong Chen

Kao-Cheng Lin

Tsung-Chieh Tsai

Yung-Chen Chien

Chien-Chi Tien

Shu-Yi Ying

Jung-chan Yang

Sheng-hsiung Chen

Jin-Wei Xu

Wei-Guo Chang

Yun-Xiang Lin

Wen-Lang Wu

Meng-hung Shen

Chien-Hsing Li

Ze-Sian Lu

Chitong Chen

Tien-Yu Kuo

Ting-Wei Chou

An integrated circuit includes a first gate electrode structure extending in a first direction. The integrated circuit includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Integrated circuit having angled conductive feature

A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Integrated circuit having fins crossing cell boundary

An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

Integrated circuit, system for and method of forming an integrated circuit

An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active region extend in a first direction, and are on a first level. The first active region includes a first and second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact includes a first and second portion. The first portion overlaps the first and second drain/source. The second portion overlaps the first contact, the first and third drain/source region, and the first insulating region, and is electrically coupled to the first portion, and electrically insulated from the first drain/source region.

Integrated circuit and method of forming the same

A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h≥1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Method for generating a layout diagram of a semiconductor device including power-grid- adapted route-spacing

A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.

Variable-sized active regions for a semiconductor device and methods of making same

An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Integrated circuit and method of manufacturing same

A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.

Semiconductor device having power rail with non-linear edge

A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

Semiconductor device with increased unity density

An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.

Methods of resistance and capacitance reduction to circuit output nodes

An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Integrated circuit structure

A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.

Method of designing an integrated circuit and system for designing integrated circuit

A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.

Different height cell subregions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Standard-cell layout structure with horn power and smart metal cut

A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Standard and engineering change order (ECO) cell regions and semiconductor device including the same

Growing community of inventors

New Taipei, Taiwan

Ting-Wei Chiang