Ememory Technology Inc.

Ting-Ting Su

Kuan-Hsun Chen

Ming-Shan Lo

Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.

Memory device for improving weak-program or stuck bit

A non-volatile memory cell is disclosed. A select gate transistor, a following gate transistor, and an antifuse varactor are coupled in series on an active area. The following gate transistor is disposed between the select gate transistor and the antifuse varactor. A first ion well and a second ion well having the first conductivity type are provided in the active area. The following gate transistor partially overlaps with the first ion well. The second ion well has a doping concentration that is smaller than that of the first ion well.

Nonvolatile memory cell capable of improving program performance

A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.

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Taipei, Taiwan

Ting-Ting Su