Nan Ya Technology Corporation

Chanpin Medtak Co., Ltd.

Ting-Shuo Hsu

Chih-Jen Chen

Chih-Wei Shen

Chuan-Jen Chang

Fon-Yih Tsuang

Chang-Jung Chiang

Yueh-Ying Hsieh

Po-Yi Liu

The present disclosure provides a spinal fixation device, including a spinal fixation pedicle screw and an outer oval sheath. The spinal fixation device is provided with at least one locking structure and the outer oval sheath is locked to the spinal fixation pedicle screw through the at least one locking structure. The spinal fixation device can strengthen the stability of the spinal fixation pedicle screw for fixation after implantation in vertebrae during the spinal surgery.

Minimally invasive and endoscopic spinal fixation device

A word line pump device of a dynamic random access memory (DRAM) chip and a clamp circuit thereof are provided. The DRAM chip receives a first voltage and a second voltage from outside, and the first voltage is smaller than the second voltage. The clamp circuit clamps a word line voltage to the second voltage in response to the word line pump device not receiving a power supply voltage.

Word line pump device of dynamic random access memory chip and clamp circuit thereof

A voltage generating device includes a clock signal generator, a voltage regulator and a pump circuit. The clock signal generator generates a clock signal according to an enable signal. The voltage regulator generates and adjusts a first voltage according to a reference voltage and the enable signal. The pump circuit receives the clock signal, the first voltage and a second voltage, wherein the pump circuit performs a voltage pump operation to generate an output voltage based on the clock signal according to the first voltage and the second voltage. The output voltage equals to a summation of the first voltage and the second voltage.

Memory device, voltage generating device and voltage generating method thereof

A voltage generator and a voltage generating method are provided. The voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a passing circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive the clock signal to generate a first pump voltage. The oscillator is configured to provide the clock signal. The passing circuit is configured to receive the clock signal, a power-on detection signal and an external command. The voltage detector is configured to receive an operation voltage, and generate the power-on detection signal by detecting the operation voltage. The passing circuit determines whether to transmit the clock signal to the second charge pump circuit or not to activate or deactivate the second charge pump circuit.

Voltage generator and voltage generating method thereof

A memory device includes an input pad, a first rank, a second rank, a first voltage detector, and a second voltage detector. The input pad is configured to receive an input voltage. The first voltage detector is coupled to the input pad, the first voltage detector is configured to receive the input voltage, and the first voltage detector is configured to transmit the input voltage to the first rank. The second voltage detector is coupled to the first voltage detector through a first through-silicon via, the second voltage detector is configured to receive the input voltage, and the second voltage detector is configured to transmit the input voltage to the second rank according to a control signal transmitted from the first voltage detector through the first voltage detector, so as to decide a state of the second rank.

Memory device

The memory apparatus includes a plurality of memory chips and a plurality of temperature sensors. The memory chips are coupled to each other. The temperature sensors are respectively disposed on the memory chips. One of the memory chips is configured to be a master memory chip, and a first temperature sensor of the master memory chip is enabled to sense an ambient temperature. The master memory chip generates a refresh rate control signal according to the ambient temperature and controls refresh rates of all of the memory chips.

Memory apparatus and refresh method thereof

A pump circuit is disclosed. The pump circuit includes a first pump core circuit and a second pump core circuit. The second pump core circuit is coupled to the first pump core circuit. When a voltage value of a power source input to the pump circuit is not lower than a threshold voltage value, the first pump core circuit is operated and the second pump core circuit is not operated. When the voltage value of the power source is lower than the threshold voltage value, the first pump core circuit and the second pump core circuit are operated, so that a current value of the output current transmitted by the pump circuit is not lower than a threshold current value.

Pump circuit, pump device, and operation method of pump circuit

A post package repair (PPR) method is disclosed. The PPR method includes the following operations: receiving a first PPR signal and a second PPR signal, in which the first PPR signal corresponds to a first PPR mode, and the second PPR signal corresponds to a second PPR mode; generating a first valid signal and a second valid signal according to the first PPR signal and the second PPR signal, in which only one of the first valid signal and the second valid signal comprises a valid information when both of the first PPR signal and the second PPR signal comprise an enabled information; in which when the first valid signal comprises the valid information, the first PPR mode is executed, and when the second valid signal comprises the valid information, the second PPR mode is executed.

Post package repair method and post package repair device

A voltage switching device, an integrated circuit device, and a voltage switching method are provided. The voltage switching device includes a reference voltage generator generating a first reference voltage and a second reference voltage, a fuse system coupled to a circuit device, and a switch circuit coupled to the reference voltage generator, the fuse system, and the circuit device. The fuse system generates a first enable signal and a second enable signal according to an input signal from a circuit device. The switch circuit transmits the first reference voltage or the second reference voltage to the circuit device according to the first enable signal and the second enable signal from the fuse system.

Voltage switching device, integrated circuit device and voltage switching method

The present disclosure provides a charge pump system and a method of operating the same. The charge pump system includes a first pump circuit, a second pump circuit and a control device. The first pump circuit is configured to operate in a first voltage domain. The second pump circuit is configured to operate in a second voltage domain different from the first voltage domain. The control device is configured to selectively enable one of the first pump circuit and the second pump circuit based on an operating environment, wherein the one of the first pump circuit and the second pump circuit provides a pump voltage.

Voltage system providing pump voltage for memory device and method for operating the same

The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.

DRAM and method of designing the same

A voltage-stabilizing circuit includes a voltage-dividing module, a first stabilizing module and a second stabilizing module. The voltage-dividing module is configured to generate a plurality of reference voltages. The voltage-dividing module includes a plurality of resistors and a transistor unit. The transistor unit is coupled to the plurality of resistors and is configured to complementarily adjust resistances of the plurality of resistors. The first stabilizing module is coupled to the voltage-dividing module and is configured to generate a first stabilizing voltage. The first stabilizing voltage is equal to a middle one of the plurality of reference voltages. The second stabilizing module is coupled to the voltage-dividing module and is configured to generate a second stabilizing voltage. The second stabilizing voltage is equal to one of the plurality of reference voltages other than the middle one.

Voltage-stabilizing circuit, DRAM, and method for stabilizing a bit line voltage

The present disclosure provides a pump circuit comprising a plurality of first enabling modules. Each of the plurality of first enabling modules is configured to generate a first enable signal and includes a first voltage input, a first comparing unit, a first digital logic gate and a second digital logic gate. The first comparing unit is coupled to the first voltage input and is configured to compare a voltage of the first voltage input with a first reference voltage. The first digital logic gate is coupled to the first comparing unit and is configured to implement a logical operation. The second digital logic gate is coupled to the first digital logic gate and is configured to implement a logical negation. Each of the plurality of first enabling modules generates the first enable signal when the voltage of the first voltage input is less than the first reference voltage.

Pump circuit in a dram, and method for controlling an overall pump current

The present disclosure provides a pump circuit comprising a temperature-sensing module, an oscillating module and a pumping module. The temperature-sensing module is configured to measure a temperature of a dynamic random access memory (DRAM). The oscillating module is coupled to the temperature-sensing module and is configured to generate a clock signal based on the temperature of the DRAM. The pumping module is coupled to the oscillating module and is configured to generate a pump voltage and a pump current to drive the DRAM, wherein the pump current is generated based on an oscillating frequency of the clock signal. When the temperature of the DRAM changes, the oscillating frequency of the clock signal changes based on the temperature of the DRAM, and the pump current correspondingly changes based on the oscillating frequency of the clock signal.

Pump circuit in a DRAM, and method for generating a pump current

The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a storage area and a control device. The storage area includes a memory row. The control device is configured to selectively allow the memory row to be eligible for a row-hammer refresh according to temperature of the DRAM.

Growing community of inventors

Taipei, Taiwan

Ting-Shuo Hsu