Industrial Technology Research Institute

Ting-Sheng Chen

Yung-Fa Chou

Ding-Ming Kwai

Jenn-Shiang Lai

An interrupt control device between clock domains is provided. An interrupt sharing logic is configured to receive one or more original interrupt signals and generate a combined interrupt signal. An interrupt processing logic is configured to output a processed interrupt signal to a processor according to the combined interrupt signal, so that the processor executes an interrupt service routine. When the interrupt service routine is executed, the processed interrupt signal changes to be disabled; before the interrupt service routine is completed, the processor outputs an interrupt clear signal to change the respective interrupt signal to be negated. After the interrupt processing logic detects that interrupt signal has been cleared successfully, the interrupt processing logic will generate the processed interrupt signal according to the combined interrupt signal again.

Interrupt control device and interrupt control method between clock domains

An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.

Operating method of hardwired switch

A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV.

Wafer and method for improving yield rate of wafer

A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.

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Hsinchu, Taiwan

Ting-Sheng Chen