Xilinx, Inc.

Intel Corporation

Altera Corporation

Ting Lu

Bradley L Taylor

Sean R Atsatt

Ahmad R Ansari

Andrew Martyn Draper

Hy V Nguyen

Hassan K Bazargan

William Edward Allaire

Kam-Wing Li

Shashank Bhonge

Bruce B Pedersen

Manoj R Sastry

Santosh Ghosh

Patrick J Crotty

Prakash N Iyer

Wei Yee Koay

James J Murray

Robert L Pelt

Brian L Wong

Sandeep Dutta

Eric Innis

Alok Shreekant Doshi

Yun Sum Wong

Stephen M Trimberger

Herman Henry Schmit

Sagheer Ahmad

Raghunandan Makaram

Anatoly S Belkin

Scott J Weber

Dana How

Sankaran M Menon

Weiguang Lu

Eric E Edwards

Ismed D Hartanto

Nishit Patel

Rajiv Kumar

Chin Ghee Ch'ng

Steve Tuyen Vu

James Ryan Kenny

Ching Kooi Hor

Wei Chun Lau

Kenneth Chen

Ka Bo Wong

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.

Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device

Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.

Digital signature verification engine for reconfigurable circuit devices

An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

Techniques for preventing voltage tampering of security control circuits

The present disclosure provides systems and methods for improving provision of secret data on programmable devices. An appliance receives physical unclonable function (PUF) data pertaining to an integrated circuit. Secret data is provided to the appliance from a secret vault. Public and private PUF keys are derived based upon the PUF data. Further, ephemeral public and private keys are derived by the appliance. The public and private PUF keys, along with the ephemeral public and private keys are used to establish a secure channel for programming the secret data on the programmable device.

Programmable device key provisioning

The disclosed systems and methods may secure the fuse programming process in programmable devices to reduce or eliminate malicious discovery of data (e.g., the encryption key, the configuration bitstream) stored in nonvolatile memory via side-channel attacks. A processor may generate a randomized fuse list and the fuses may be blown in the randomized order. Additionally or alternatively, the processor may randomize the wait time between programming of each fuse. Further, the processor may generate a simplified fuse list including only fuses to be blown. The disclosed security systems and methods may be used individually or in combination to prevent determination of sensitive data, such as the encryption key, by monitoring, for example, power consumption in side-channel attacks.

Side-channel attack resistant fuse programming

The present disclosure provides confidential verification for FPGA code. Confidential verification for FPGA code can include receiving the policy from a cloud service provider (CSP) computing device, wherein the policy comprises a plurality of policy requirements used to determine whether to configure the FPGA using the code, receiving the code and the code encryption key from the user computing device, determining whether the code fulfills the plurality of policy requirements, and when the code fulfills the plurality of policy requirements encrypting and integrity protect the code using the code encryption key and providing the encrypted and integrity protected code to an accelerator loader to configure the FPGA using the code.

Confidential verification of FPGA code

An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.

Techniques for protecting security features of integrated circuits

Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.

Apparatus and method for security in an integrated circuit

A system for maintaining reconfigurable partitions in an integrated device includes a first buffer having channels that store configuration data and a mask. The system also includes first decompression circuitry having a second buffer coupled to the first buffer that stores the configuration data and second decompression circuitry having a third buffer coupled to the first buffer that stores the mask. The system also includes partition maintenance circuitry that applies the mask to the configuration data after the first decompression circuitry has decompressed the configuration data and the second decompression circuitry has decompressed the mask.

Maintaining reconfigurable partitions in a programmable device

An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.

In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.

Circuit design implementations in secure partitions of an integrated circuit

In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

Error correction for interconnect circuits

A method of processor operation using an integrated circuit (IC) can include loading encrypted program code into the IC through a configuration port of the IC and decrypting the encrypted program code using configuration circuitry of the IC. Decryption of the encrypted program code can result in decrypted program code which can be provided to a target destination.

Secure processor operation using integrated circuit configuration circuitry

An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Integrated circuit with programmable circuitry and an embedded processor system

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Austin, TX, United States of America

Ting Lu