Integrated Technology Express Inc.

Ting-Li Hu

A device for generating a pair of true/complementary-phase logic signals is provided. The device comprises a single-end to true/complementary-phase signal conversion circuit, a first stage circuit and a differential amplifier. The conversion circuit receives a single-end signal and converting the single-end signal to a first pair of true/complementary-phase signals. The first stage circuit receives the first pair of true/complementary-phase signals and performing a feedback control to obtain a second pair of true/complementary-phase signals. The differential amplifier receives the second pair of true/complementary-phase signals and outputs a pair of differential signals. Therefore, the rising time/falling time of one of the pair of differential signals is synchronized with the falling time/rising time of the other of the pair of differential signals.

Differential signal pairs generator

A high-speed rail-to-rail comparator is described. The comparator has two PMOS transistors, two NMOS transistors, a current source and two voltage-dropped components. A first PMOS transistor has a source terminal coupled to a first voltage source and a gate terminal and a drain terminal coupled to each other. A second PMOS transistor has a source terminal coupled to the first voltage source, and a gate terminal of the second PMOS transistor coupled to the gate terminal of the first PMOS transistor. A first NMOS transistor has a drain terminal coupled to the drain terminal of the first PMOS transistor and a gate terminal coupled to a reference signal. A second NMOS transistor has a drain terminal of the first NMOS transistor coupled to the drain terminal of the second PMOS transistor and coupled to an output terminal. A gate terminal of the second NMOS transistor is coupled to an input terminal and a source terminal of the second NMOS transistor is coupled to a source terminal of the first NMOS transistor. A first voltage-dropped component has a positive terminal coupled to the gate terminal of the second PMOS transistor and a negative terminal coupled to the drain terminal of the second NMOS transistor. A second voltage-dropped component has a positive terminal coupled to the drain terminal of the second NMOS transistor while a negative terminal of the second voltage-dropped component is coupled to the source terminal of the second NMOS transistor.

Growing community of inventors

Taichung, Taiwan

Ting-Li Hu