Via Technologies, Inc.

Ting-Kun Yeh

Roger Lin

Sheng-Che Tsao

An-Te Chiu

Jackie Hsiung

Roy Wang

David Wang

Martin Hsu

Kuei-Lan Lin

A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.

Method and apparatus of arranging priority queue and arbitrating for memory access requests

A method and system for applying pipeline architecture to discrete cosine transform and inverse discrete cosine transform. Each of the discrete cosine transform and inverse cosine transform are divided into four phases computed by process elements. Each phase can be designed by adjusting the amount of process elements according the demand of performance.

Method and system for discrete cosine transforms/inverse discrete cosine transforms based on pipeline architecture

An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's defaults and firmware, wherein the address and data pins of the SDRAM and the flash memory are coupled with a same bus respectively, and SDRAM and flash memory are not accessed at the same time; a memory interface, connecting the address bus and data bus shared by the SDRAM and flash memory. The memory interface further comprises an arbiter, deciding which one of the access requests is executed according to the request priority. It is noticed that only one of the SDRAM or the flash memory can be accessed at one time.

Apparatus and method for memory access of sharing buses

An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.

Device and method for variable length decoding

The present invention provides a method and apparatus of adaptive de-interlacing of dynamic image, configured for calculating encoding information of a dynamic image to acquire an image shift value of field and then compare the image shift value of field with a programmable threshold. When the image shift value of field is substantially greater than the threshold, then choosing Bob algorithm for de-interlacing; otherwise, when the image shift value of field is substantially less than the threshold, then choosing Weave algorithm for de-interlacing to constitute a high-resolution motion image.

Method and apparatus of adaptive de-interlacing of dynamic image

The present invention provides a method and apparatus of adaptive de-interlacing of dynamic image, in which extraction and calculation of motion vectors contained in a macro-block being processed, the value of calculation of motion vectors being then compared with a programmable threshold; wherein the macro-block being a motion block if the value of calculation being greater than the threshold and therefore Bob algorithm being chosen for de-interlacing process. Otherwise, the macro-block being a still block if the value of calculation being less than the threshold and therefore Weave algorithm being chosen for de-interlacing process. Consequently, the process is enforced continually and a dynamic image of high image quality is constituted with block as its unit.

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Taipei, Taiwan

Ting-Kun Yeh