Realtek Semiconductor Inc.

Ting-Hsiung Wang

Yu-Lan Lo

Shu-Yi Kao

Mei-Li Yu

Ying-Chieh Chen

Meng-Jung Lee

Chia-Ling Hsu

A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Method of detecting relations between pins of circuit and computer program product thereof

A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.

Simulation method for mixed-signal circuit system and related electronic device

A computer program product stored in a non-transitory storage device of an integrated circuit (IC) timing analysis device includes: a netlist reading module for reading a netlist of an integrated circuit; a signal path analysis module for analyzing signal paths of a clock signal to generate a simplified netlist of the integrated circuit; a clock delay calculating module for calculating clock delays of the clock signal respectively corresponding to the signal paths.

Computer program product for timing analysis of integrated circuit

A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.

Method for determining interface timing of integrated circuit automatically and related machine readable medium thereof

A deadlock detection method includes: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path. A non-transitory machine readable medium stores a program code, wherein when executed by a processor, the program code enables the processor to perform the following steps: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path.

Deadlock detection method and related machine readable medium

An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added.

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Kaohsiung, Taiwan

Ting-Hsiung Wang