Macronix International Co., Ltd.

Ting-Chung Hu

Li-Jen Lee

Tai-Yao Lee

Chung-Wen Ma

Ju-Xu Lee

Ray-Lin Wan

Kong-Mou Liou

Chun-Hsiung Hung

Chun-Hung Lin

Tien-Ler Lin

Tom D Yiu

Chih-Wei Chen

Fuchia Shone

Yao-Wu Cheng

Chu-Hung Lin

A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

Technique for increasing endurance of integrated circuit memory

The present application discloses methods to provide defect management, wear leveling and data security to a mass storage system implemented using flash memory. The flash memory is organized into a plurality of blocks. Each block has a special region for storing its attributes. In defect management, defects arising from manufacturing and on-the-fly defects are scanned. Defective blocks are marked by altering its attributes. The present application also discloses a wear leveling method in which the difference between the number of erasures of any two blocks (except the defective blocks) is within a predetermined value. The present application further discloses a new error detection and correction method. The same data is stored in two separate memory locations. The content of these two locations are later 'ored' or 'anded' together (depending on the nature of error giving rise to the error) to recover the correct data.

Method and system for managing a flash memory mass storage system

An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled. Consequently, there is a constant supply of blocks in the second category. In another embodiment of the present invention, a new category is developed to handle random writing to the working blocks.

Flash memory mass storage system

Technique for reconfiguring a high density memory

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Milpitas, CA, United States of America

Ting-Chung Hu