Taiwan Semiconductor Manufacturing Comp. Ltd.

Ting-Chun Wang

Shiu-Ko JangJian

Cheng-Ta Wu

Wei-Ming You

Chia-Yang Wu

Chi-Cherng Jeng

Cheng-Wei Chen

Yung-Si Yu

Ying-Lang Wang

Chi-Wen Liu

Yu-Ku Lin

Chung-Ren Sun

Kei-Wei Chen

Jun-Nan Nian

Shih-Tzung Chang

Yu-Ting Lin

Szu-An Wu

Lun-Kuang Tan

Chih-Nan Wu

Min Hao Hong

Shiu-Ko Jangjian

Yi-Hsien Lee

Hsi-Kuei Cheng

Che-Hao Chang

Yao-Hsiang Liang

Ming-Te Chen

Sheng-Wen Chen

Kuo-Hsiu Wei

Chun-Che Lin

Pu-Fang Chen

Tsung-Han Wu

Yu-Ren Peng

Chia-Hung Chung

Ing-Ju Lee

Hong-Yi Wu

Liang-Yu Yen

Chung-Yi Huang

Tung-Ti Yeh

I-Che Huang

Yuan-Nien Chen

Yu-Ting Hsiao

Jun-Jie Cheng

Ya Wen Wu

Chun-Chang Chen

Chun Che Lin

Shih-Ho Lin

Yao-Wen Hsu

Yung-Hsiang Chan

Chuan-Pu Liu

Hsien-Ping Feng

Kuo-Hsien Cheng

Po-Kai Hsiao

Po-Kang Ho

Chu-Chang Chen

Yi-Lang Wang

Yung-Yu Wang

Hui Mei Jao

Ming-Wen Chen

Chun-Tse Lin

Yu-Kin Lin

Aaron Cheng

Shiu-Ko Jang-Jian

J W Wu

Chia-Ying Tsai

Tsung Han Wu

Wu-Chang Lin

Hui-Mei Jao

Ching-Hwan Su

Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

Flat STI surface for gate oxide uniformity in Fin FET devices

A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the contact layer passes through the first barrier layer, the first barrier layer passes through the second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of a sidewall of the first barrier layer and exposes a first lower portion of the sidewall of the first barrier layer, and the sidewall faces away from the contact layer.

Semiconductor device structure with barrier layer

A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Conductive contact having barrier layers with different depths

A semiconductor device structure is provided. The semiconductor device structure includes a contact layer over a metal silicide layer. The contact layer extends through a first dielectric structure. The semiconductor device structure includes a first metal nitride barrier layer over sidewalls of the contact layer. The first metal nitride barrier layer is directly adjacent to the first dielectric structure. The semiconductor device structure includes a second metal nitride barrier layer partially between the contact layer and the metal silicide layer and partially between the contact layer and the first metal nitride barrier layer. The metal silicide layer is below the first metal nitride barrier layer and the second metal nitride barrier layer.

A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer. The first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, the contact layer passes through the first barrier layer and extends into the dielectric structure, and the first barrier layer passes through the second barrier layer and extends into the dielectric structure.

A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

Method for controlling electrochemical deposition to avoid defects in interconnect structures

An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

Electrochemical plating system and method of using

A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

FinFET gate structure

A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

Semiconductor device structure with barrier layer and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.

Semiconductor structure and method for forming the same

Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.

Metal gate stack having TaAlCN layer

Conductive contact having staircase barrier layers

Growing community of inventors

Tainan, Taiwan

Ting-Chun Wang