Mediatek Corporation

Ting-Cheng Hsu

Yen-Yu Lin

Hong-Kai Hsu

Wei-Lun Wan

Chang-Fu Lin

Chih-Wei Ko

A patching device and method thereof for patching a firmware function by a patch function. When a fetch address from a processor does not correspond to the firmware function, the patching device outputs an instruction of the fetch address to respond to the processor. When the fetch address corresponds to the replaced firmware function, the patching device outputs an artificial instruction to respond to the processor. The artificial instruction is one of series of machine codes corresponding to a plurality of patch intermediary instructions utilized to direct the processor to jump to the beginning address of the patch function.

Patching devices and methods thereof for patching firmware functions

A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Processing modules with multilevel cache architecture

A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information stored in control registers. A cache hit detection circuit includes an address register storing the data access address, tag memories storing tag data of the data access address, a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal, and address comparators each comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match. The tag data is adjusted to a predetermined address by the data processing device, which is the highest address of memory space of the processor.

Growing community of inventors

Hsinchu, Taiwan

Ting-Cheng Hsu