International Business Machines Corporation

Tina Babinsky

Silvia Melitta Mueller

Cedric Lichtenau

Michael Klein

Klaus Michael Kroener

Andreas Wagner

Udo Krautz

Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n&#xd7;P&#xd7;Q+m&#xd7;R&#xd7;S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Multiply-add operations of binary numbers in an arithmetic unit

A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113&#xd7;113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.

Fused-multiply-add floating-point operations on 128 bit wide operands

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Steinenbronn, Germany

Tina Babinsky