Intel Corporation

Tin-Fook Ngai

Hong Wang

Perry H Wang

John P Shen

James Paul Held

Partha Kundu

Raya Leviathan

Edward Thomas Grochowski

Jamison D Collins

Youfeng Wu

Sara S Baghsorkhi

Victor W Lee

Jayashankar Bharadwaj

Albert Hartono

Nalini Vasudevan

David J Sager

Koichi Yamada

Ron Gabor

Joseph Nuzman

Shlomo Raikin

Daehyun Kim

Ruchira Sasanka

Suresh Srinivas

Jayaram Bobba

Ho-Seop Kim

Omar M Shaikh

Zhaohui Du

Leeor Peled

Yingzhe Shen

Howard Chen

Zhao Hui Du

Chu-Cheow Lim

Chunxiao Lin

Jason A Domer

Chao Zhang

Li Liu

Guangjie Li

Hu Tiger Chen

Gansha Wu

Jeffrey J Cook

Xiangbin Wu

Xiaocheng Zhou

Senjie Zhang

Sai Luo

Xuebin Yang

Ed Grochowski

Peinan Zhang

Buqi Cheng

Kevin W Rudd

Shunyu Zhu

Bu Qi Cheng

Jeffery J Cook

Jamison D Colins

Kim Daehyun

Shiwei Liao

Kang Zhao

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

Multicore memory data recorder for kernel module

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Method and system to provide user-level multithreading

Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate

Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.

Memcached systems having local caches

Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.

Partial vectorization compilation system

Embodiments of an enhanced Node B (eNB) configured for use in a cooperative radio access networks (C-RAN) and method for central baseband unit (BBU) processing are generally described herein. In some embodiments, the eNB may include a baseband unit (BBU) processing pool comprising a plurality of processing units. The BBU processing pool is configured to share the processing load of several sectors. A control unit may monitor the processing load of the processing units and perform dynamic load sharing by migrating the baseband processing between the processing units without changing a carrier used by user equipment operating with a sector.

Cooperative radio access network with centralized base station baseband unit (BBU) processing pool

An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

Apparatus and method for vectorization with speculation support

Growing community of inventors

San Jose, CA, United States of America

Tin-Fook Ngai