Fairchild Semiconductor Corporation

National Semiconductor Corporation

Timwah Luk

Chung-Lin Wu

Janusz Bryzek

Ahmad Ashrafzadeh

Etan Shacham

Maria Clemens Ypil Quinones

John R Constantino

Robert L Krause

Yong Liu

Murray J Robinson

Christopher C Joyce

Scott Irving

Terry J Johnson

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Isolation between semiconductor components

A chip with resistive, metallic strain gauges distributed on surfaces on and buried within the chip. Also, vertically arranged vias and vertical thin film resistive strain gauges are described. The resistive strain gauges can be multiplexed wherein strain can be measured across the topology of the chip in each of the top, bottom and buried layers and any vertical strain. The resistive strain gauges may be in serpentine patterns and may be arranged on via or on vertical edges of grooves that extend from an upper or lower surface of the chip to buried layers. In this fashion, the distributed strain gauges may be used to map the strain throughout the body of a chip. A Kelvin bridge may be used to measure the strain, but other such measuring techniques and devices may be used.

Die scale strain gauge

An improved Schottky transistor structure (6), including a bipolar transistor structure (7) and a Schottky diode structure (8), is formed by retrograde diffusing relatively fast diffusing atoms to form a localized retrograde diode well (9) as the substrate for the Schottky diode structure. An expanded buried collector layer (11) formed of relatively slow diffusing atoms underlies the base and collector regions of the bipolar transistor structure (7) and the retrograde diode well (9). A diode junction (10) is formed by expanding the base contact of the bipolar transistor structure to include the surface of the retrograde diode well. Preferably, the diode junction is a Platinum-Silicide junction. The improved Schottky transistor structure may be formed as part of a bipolar junction transistor fabrication process or a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as the buried collector layer of the bipolar transistor structure and the retrograde diode well may be formed at the same time as the sub-emitter collector region of the bipolar transistor structure. The buried collector layer definition mask is also a buried diode layer definition mask, the sub-emitter collector region definition mask is also a retrograde diode well definition mask, and the bipolar contacts definition mask is also a diode junction contact definition mask.

Retrograde NWell cathode Schottky transistor and fabrication process

A temperature compensated ECL gate (20) with each gate circuit resistance formed by a pair of opposite polarity temperature coefficient resistors. A first gate transistor element (Q1) and a second gate transistor element (Q2) coupled at a common emitter coupling (12) provide alternative collector current paths from high potential (V.sub.cc) through a first gate transistor collector path with collector resistance (R11,R12) and a gate transistor collector path with collector resistance (R21,R22). A current source transistor element (Q3) is coupled between the common emitter coupling (12) of the gate transistor elements and low potential (V.sub.EE) through current source resistance (R31,R32). The resistances of the ECL gate each include a positive temperature coefficient silicon first resistor (R11,R21,R31) and a negative temperature coefficient low capacitance polysilicon second resistor coupled (R12,R22,R32) in series. The sum of the resistances of the first and second resistors is selected to providing the respective circuit resistance of the ECL gate and the ratio of the resistances of the first and second resistors is selected according to the temperture characteristics of the current source voltage generator and the temperature characteristics of the first and second resistors for substantial temperature compensation of the gate current and signal voltage swing over a specified temperature range. The temperature compensating pair of opposite polarity temperature coefficient resistors is also applicable for temperature compensation at active nodes of TTL and STL circuits.

Temperature compensated bipolar circuits

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Falmouth, ME, United States of America

Timwah Luk