Hypres, Inc.

Timur V Filippov

Deepnarayan Gupta

Alexander F Kirichenko

Oleg A Mukhanov

Alex Kirichenko

A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.

Superconducting multi-bit digital mixer

The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic.

Ultra fast circuitry for digital filtering

A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

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Mahopac, NY, United States of America

Timur V Filippov