Intel Corporation

Timothy Y Kam

Sandeep Ahuja

Krishnakanth Venkata Sistla

Stephen H Gunther

Tessil Thomas

Robin A Steinbrecher

Phani Kumar Kandula

Jay D Schwartz

Michael Berktold

Howard Chin

Seongwoo Kim

Avinash Sodani

Rajat Agarwal

Meenakshisundaram Chinthamani

Michael Kishinevsky

Jinho Suh

Loic Henry-Greard

In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

Apparatus and method to provide a thermal parameter report for a multi-chip package

Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

Thermal throttling of electronic devices

Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Mechanisms for enabling power management of embedded dynamic random access memory on a semiconductor integrated circuit package

Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package

Embodiments of the present invention generate equations that model a synchronous circuit that contains sequential elements, which may include transparent elements, and a plurality of multiple-phase clocks. Phase-related information is assigned to nodes of the circuit. The phase-related information describes input and output characteristics at nodes of the circuit as the characteristics relate to clock phases. Equations are formed that model signals at the circuit nodes based on the phase-related information.

Modeling of phase synchronous circuits

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Portland, OR, United States of America

Timothy Y Kam