Tektronix, Inc.

Timothy W Slate

Bruce J Penney

Patten A Emmons

A nonvolatile memory protection system for a microprocessor system having a common address bus, to which a nonvolatile memory is connected, interposes a controller connected to the common address bus between the commands generated by the microprocessor and the nonvolatile memory. The controller generates valid commands for the nonvolatile memory upon receiving a predetermined sequence of commands from the microprocessor, disabling the nonvolatile memory in the absence of valid commands. A power protect circuit connected between the microprocessor system power supply and the nonvolatile memory provides a disable signal to the nonvolatile memory during power up and power down of the microprocessor system.

Nonvolatile memory protection

A digital phase-locked loop maintains a clock signal in a predetermined phase and frequency relationship with an input video signal having a repeating signal element, such as horizontal sync pulses and/or color burst signals. The clock signal is generated by a voltage controlled oscillator, the frequency of which depends on an input digital control signal. The input video signal is sampled by an analog-to-digital converter at the clock signal frequency to generate a succession of digital words representing the amplitudes of successive samples. A portion of the successive digital words is stored in a memory, the access to which is controlled so that the samples representing the repeating signal element are stored and then read out for processing by a microprocessor. The digital control signal from the microprocessor which is input to the oscillator represents the difference between the actual phase and frequency relationship between the clock signal and the repeating signal element and the desired predetermined phase and frequency relationship so that the oscillator frequency is varied to attach such predetermined phase and frequency relationship.

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Portland, OR, United States of America

Timothy W Slate