Taiwan Semiconductor Manufacturing Comp. Ltd.

Timothy Vasen

Gerben Doornbos

Marcus Johannes Henricus Van Dal

Matthias Passlack

Georgios Vellianitis

Martin Christopher Holland

Blandine Duriez

Mark Van Dal

Chao-Ching Cheng

Lain-Jong Li

Tse-An Chen

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Method of manufacturing a semiconductor device and a semiconductor device

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

Methods of manufacturing a field effect transistor using carbon nanotubes and field effect transistors

The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

Gate all around semiconductor structure with diffusion break

Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

Wafers for use in aligning nanotubes and methods of making and using the same

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

Tunnel field-effect transistor with reduced trap-assisted tunneling leakage

Semiconductor structure with diffusion break and method

In a method, a charged metal dot is deposited on a first position of a surface of a semiconductor substrate. Then, a charged region is formed on a second position of the surface of the semiconductor substrate, thereby establishing of which an electric field direction from the first position toward the second position. The first position is spaced apart from the second position by a distance. Thereafter, a precursor gas flows along the electric field direction on the semiconductor substrate, thereby forming a carbon nanotube (CNT) on the semiconductor substrate.

Method of forming semiconductor device having carbon nanotube

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an interlayer dielectric (ILD) layer is formed over the doped source/drain region and the sacrificial gate structure, a source/drain opening is formed by patterning the ILD layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

Field effect transistor using carbon nanotubes

A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

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Tervuren, Belgium

Timothy Vasen