International Business Machines Corporation

Timothy V Lee

Jeffrey S Gordon

Daniel C Kuhl

Joseph K Farrell

Tony E Parker

Gary B Hoch

Robert V Jenness

Rex E McCrary

Stephanie P Payne

Daniel Petkevich

Hai V Pham

Don S Keener

Arthur L Chin

Gregory J Moore

Eric S Stine

Serafin J Eleazar-Garcia, Jr

A high performance serial bus operating at multiple transmission rates is disclosed. The serial bus is able to automatically generate data response packets for return to a requesting node. The automatic packet generation uses the source and destination information to generate a return destination packet for directing the requested data to the request source destination. Since the bus network is capable of operating at several different transmission rates, the speed at which the data request packet was transmitted is used for retransmitting the data requested back to the source node requesting the data.

System for reformatting a response packet with speed code from a source

A computer system allows for a hardware structure to participate in the transmission of P1394 packets, which are comprised of command or data blocks from linked list structures in a system memory, is disclosed. The system is able to provide dynamic appending of these command or data blocks to the link list while they are being operated upon. This provides an efficient transaction layer operation, which minimizes signalling between the link list operator or control code, and other hardware features.

Method and system for dynamically appending a data block to a variable

Disclosed is an arrangement for 'seamlessly' integrating telephone services relative to primitive analog telephone equipment into general purpose computer systems. The integration is effected through present 'secondary' adaptation of data link control adapter devices which are adapted primarily for coupling such computer systems to high speed data communication links for transmission and reception of digital data. This permits general resources of the computer system (keyboard, memory, disk drives, etc.) to be used for specific applications associated with telephone services. Presently described link control devices have a telephone attachment port which couples through analog-to-digital conversion circuits to a primitive analog telephone (no dial or keys). Such devices operate normally in time division multiplex to process communication data between a computer (host) system and data link ports. The present adaptation includes a host programmable time division switch circuit within the control device, which can be conditioned dynamically to route digitized telephone signals directly between its data link and telephone ports, whereby telephone signals can be transmitted isochronally between a local user of the host system and a remote telephone, over a telephone network connection, while data signals are being transferred in either direction between the host system and equipment at the remote telephone station over the same connection.

Adapter for interfacing a computer to a multichannel digital network,

This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

Personal computer with programmable threshold FIFO registers for data

Subject burst time division multiplex interface connects circuits which perform 'layer 1 (L1)' line control functions relative to a data communication network with devices which perform 'Layer 2 (L2)' link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols; e.g. High-Level Data Link Control (HDLC), Link Access Procedure-D (LAP-D), clear voice, etc. Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.

Burst time division multiplex interface for integrated data link

A 'single-chip' integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes. Synchronous units which handle data are configured to form plural stage pipelines, in each direction of communication, which eases timing requirements at the bus interface. Status information is stored queued in memory unit storage spaces dedicated to the channels; each queue configured so that the system CPU can retrieve status information representing plural events in one channel in one coherent bus operation. The device is partitioned further to provide discretely separate internal paths for transferring service and data signals relative to the system. Service signal transfers to and from system CPU and directed by the CPU. Data signal transfers to and from system memory are directed by a DMA control unit in the device.

Data link controller with autonomous in tandem pipeline circuit elements

An integrated data link control device (IDLC) interfaces between a host computer system and external channels in a communication network. The device contains multiple internal channels allocatable individually to interface to the external channels, each internal channel having internal buffer memory reserved to it for storing data signals handled by it. The device also includes facilities for selectively configuring groups of its internal channels into 'extended channels', some of which are termed Hyper Channels. Channels in each extended channel group interface collectively and in time coordination to one external channel, presenting an effective bandwidth to the external channel which is greater than the bandwidth of any single internal channel. One channel in each group is designated as a reference channel for the group, and all data signals transferred between the group and the assigned external channel are funneled through only the buffer memory assigned to the respective reference channel; in order to ensure that such signals are transferred between the external channel and the host system in their correct 'message' sequence.

Data link controller with channels selectively allocatable to hyper

An improved multi-channel direct memory access (DMA) controller for data processing systems provides adaptive pipelining and time overlapping of operations performed relative to communication channels. Registers and resources used to pipeline communication data and control signals relative to plural channels are adaptively shared relative to a single channel when command chaining is required relative to that channel. In command chaining a plural word command, termed a Device Control Block (DCB), is fetched from an external system memory via a bus having severe time constraints relative to potential real time requirements of the channels. Pipelining and time overlapping of channel operations, relative to plural channels, increases the effective rate of transfer at the bus interface to the system memory, and thereby allows for the controller to be used for applications in which throughput requirements and bus access constraints could otherwise conflict.

Direct memory access controller with adaptive pipelining and bus control

A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A 'resource manager' element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.

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Boca Raton, FL, United States of America

Timothy V Lee