Burr-brown Corporation

Texas Instruments Corporation

Timothy V Kalthoff

Rodney T Burt

Binan Wang

James Lee Todsen

Miaochen Wu

R Mark Stitt, Ii

Bernd M Rundel

Ka Yin Leung

Ralph Oberhuber

Jimmy R Naylor

Mark Allan Shill

Michael A Wu

Jeffrey David Johnson

David A Heisley

Gregory Stewart Waterfall

Yan Wang

A switched-capacitor circuit (orA) samples a first signal (V) onto a first capacitor (Cor C) by switching a top plate thereof via a summing conductor () to a first reference voltage (V) and switching a bottom plate thereof to the first signal. A second signal (V) is sampled onto a second capacitor (Cor C) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (Vor V), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.

Zero-power sampling SAR ADC circuit and method

Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.

Circuits and methods to minimize nonlinearity errors in interpolating circuits

A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected. For example, a filter path can be suitably configured with a multiplier component such that an equalized gain can be realized for each filter path. In addition, the various filters of the digital filter circuit can be configured within the parallel arrangement to provide reduce layout requirements through the sharing of components. For example, a second filter can share at least two integrators with the third filter, and the first filter can share at least one integrator with the third filter. Further, the digital filter can be suitably configured for operation in various industrial applications. For example, the first filter can be suitably configured with a notch filter configured to replace the first, third and other odd harmonic notches of the first filter.

Fast-settling digital filter and method for analog-to-digital converters

A capacitor array is configured to negate or cancel the voltage coefficient of the capacitors within the array, and thus reduce and/or eliminate the voltage coefficient non-linearities present within the A/D converter. In the capacitor array, a first capacitor is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient non-linearities of the first capacitor can be suitably canceled by the inverse voltage coefficient non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.

Capacitor array having reduced voltage coefficient induced non-linearities

A touch screen digitizing system includes a touch screen unit including a first resistive sheet with opposed x&plus; and x&minus; terminals and a second resistive sheet with opposed y&plus; and y&minus; terminals, and an ADC having first and second reference input terminals. A first switch is coupled between a first reference voltage and the x&minus; terminal, and a second switch is coupled between the x&plus; terminal and a second reference voltage for energizing the first resistive sheet. A third switch is coupled between the first reference voltage and the y&minus; terminal, and a fourth switch is coupled between the y&plus; terminal and the second reference voltage for energizing the second resistive sheet. Switching circuitry couples an input of the ADC to the y&plus; terminal while the first resistive sheet is energized and the second resistive sheet is not energized, and also couples the input to the x&plus; terminal while the second resistive sheet is energized and the first resistive sheet is not energized. The structure provides continuous calibration of the full-scale analog touch screen output of the full-scale digital output of the ADC irrespective of sharply different variations in resistances of the switches and resistive sheets.

Touch screen measurement circuit and method

A digital-to-analog converter includes a resistive divider network including a plurality of series resistors of resistance R and a plurality of shunt resistors of resistance 2R' and a circuit for switching a shunt resistor of the resistive divider network in the digital-to-analog converter to either of first and second reference voltages. The switching circuit includes a first switch MOSFET coupling the low reference voltage to the shunt resistor, and a second switch MOSFET coupling the shunt resistor to the high reference voltage. First and second switch control circuits adjust the on resistances of the first and second switch MOSFETs to be proportional to the resistances of first and second reference resistors, which have the same temperature coefficient as the resistors of which the divider network is composed. The on resistance of each of the first and second switch MOSFETs is equal to R.sub.ONi, and the resistance 2R' is equal to 2R-R.sub.ONi. The on resistances do not need to be binarily scaled.

R/2R' ladder switch circuit and method for digital-to-analog converter

A programmable gain delta sigma analog-to-digital converter includes an analog input terminal receiving an analog input voltage, a charge summing conductor, an input capacitive switching circuit, and a feedback reference capacitive switching circuit coupled to the charge summing conductor. An integrator is coupled between the charge summing conductor and a comparator which supplies a stream of digital pulses to a digital filter that produces a digital number representing the analog input voltage. The feedback reference capacitive switching circuit includes a plurality of reference sampling capacitors, selectively coupling charge between a feedback reference voltage source and an integrating capacitor of the integration in response to a programmable gain control circuit so as to provide a selected gain for the analog-to-digital converter. The sampling rate of the capacitive switching circuits is adjusted proportionally to the selected gain to improve the dynamic range of the analog-to-digital converter.

Programmable gain for delta sigma analog-to-digital converter

A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Capacitor array having user-adjustable, manufacturer-trimmable

An integrating circuit includes an operational amplifier and an integrating capacitor which is decoupled from the output of the operational amplifier and precharged to a positive reference voltage before each integration cycle. During each integration cycle the operational amplifier output decreases from the reference voltage toward but not below ground. This allows the operational amplifier to be included as a front-end integrator to a delta-sigma analog-to-digital converter that is powered only by a single power supply. In the described embodiment, the output is coupled to an input of an auto-zeroing stage which provides negative feedback to stabilize the operational amplifier when the integrating capacitor is disconnected during precharging and a bandwidth control input which couples a larger compensation capacitance to reduce the bandwidth during integration to reduce RMS noise. In the described embodiment, a correlated double sampling capacitor is discharged to zero while the integrating capacitor is precharged and kT/C error and charge injection error voltages of opposite polarity are stored on both the integrating capacitor and the correlated double sampling capacitor. The correlated double sampling capacitor is switched into the feedback of the operational amplifier in series with the integrating capacitor to automatically cancel the error voltages and present a more accurate input to the delta-sigma analog-to-digital converter.

Current-to-voltage integrator for analog-to-digital converter, and method

A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator. The switched capacitor input sampling circuit also includes a first switch coupled between the first input terminal and a first conductor, a second switch coupled between the second input terminal and a second conductor, a third switch coupled between the first conductor and a bias voltage conductor, a fourth switch coupled between the second conductor and the bias voltage conductor, a first input capacitor coupled between the first conductor and a third conductor, a second input capacitor coupled between the second conductor and a fourth conductor, a fifth switch coupled between the third and fourth conductors, a sixth switch coupled between the third conductor and the first charge summing conductor, and a seventh switch coupled between the fourth conductor and the second charge summing conductor.

Switched capacitor input sampling circuit and method for delta sigma

Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier. A control circuit receives a resolution control signal and changes both the sampling frequency control signal and a bias control signal in response to the resolution control signal so as to achieve a predetermined tradeoff between resolution of the digital output and dc power dissipation of the analog-to-digital converter.

Delta sigma analog-to-digital converter having programmable

A current integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to receive a ground voltage and an inverting input coupled to an input conductor, with an input current flowing through the input conductor, an integrating capacitor having a first terminal coupled by an isolation switch to the input conductor. A reset circuit is coupled to the integrating capacitor and is operative to reset the integrating capacitor before each integrating cycle. A digital-to-analog converter, which may be a CDAC, has an output coupled to a second terminal of the integrating capacitor, which may constitute the capacitors of the CDAC. An input of a tracking circuit is coupled to an output of the comparator to produce digital signals on digital inputs of the digital-to-analog converter to maintain the input of the comparator close to a virtual ground voltage, a digital signal on the inputs of the digital-to-analog converter representing the integral of the input current. The isolation switch opens during transients occurring on a charge summing conductor during digital-to-analog converter update and reset operations. An internal reset switch is coupled between a reference conductor and the first level. An external switch is coupled between ground and the input conductor.

Isolating a CDAC array in a current integrating ADC

A current-integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to a ground voltage and an inverting input coupled to an input conductor carrying an analog input current. An integrating capacitor having one terminal coupled to the input conductor and another terminal coupled to an output of a digital-to-analog converter. A tracking circuit is coupled to an output of the comparator to apply digital signals to inputs of the digital-to-analog converter to maintain the inverting input close to a virtual ground voltage. A digital filter filters the digital signals to produce a digital output signal that precisely represents the input current. The tracking circuit includes a first integrator having an input coupled to the output of the comparator, a predictor circuit producing average step rate information in response to an output of the first integrator, and a second integrator producing the digital signals in response to the predictor means to produce accurate tracking. The integrating capacitor and digital-to-analog converter are included in a CDAC.

Precision digitized current integration and measurement circuit

Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor. The second transistor produces a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage. A current mirror receives a collector current of the second transistor. The current mirror produces in the second conductor a correction signal substantially equal and opposite to the first non-linear current.

Circuit technique for cancelling non-linear capacitor-induced harmonic

A stable, low noise, low output impedance CMOS reference voltage circuit includes a CMOS/bipolar band gap circuit producing a reference voltage on the source of a source follower transistor driven by an output of a CMOS differential amplifier which maintains a V.sub.THERMAL voltage across the bases of a pair of emitter follower transistors driving the inputs of the CMOS differential amplifier. A power supply noise rejection circuit includes a cascode MOSFET coupling the drain of the source follower output transistor to a positive power supply voltage conductor. A current mirror circuit greatly attenuates any power supply voltage perturbations before they reach the gate of the cascode MOSFET. A unity gain buffer includes a CMOS differential amplifier input stage with one input coupled to the output of the source follower transistor and an output driving a CMOS operational transconductance amplifier.

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Tucson, AZ, United States of America

Timothy V Kalthoff