Nvidia Corporation

Hgst Netherlands, B.v.

Lucent Technologies Inc.

Avaya Inc.

Oracle America, Inc.

Avaya Technology LLC

Western Digital Technologies, Inc.

Cigital, Inc.

Timothy Tsai

Stephen William Keckler

Navjot Singh

Cyril Guyot

Siva Kumar Sastry Hari

Zvonimir Z Bandic

Michael Brendan Sullivan

Siva Hari

Sachin Garg

Brian Matthew Zimmer

Iuri Frosio

Anima Anandkumar

Tomohiro Harayama

Zahra Ghodsi

Kenny C Gross

Kalyanaraman Vaidyanathan

Robert Eugeniu Mateescu

Qingbo Wang

Saurabh Bagchi

Shad Henry Thorstenson

Alejandro Jose Troccoli

Yu-Sung Wu

Michael Sullivan

Luiz M Franca-Neto

Takaki Nakamura

Reinhard P Klemm

Hitoshi Kamei

Frank R Chu

Jeffrey Michael Pool

Saurabh Jha

Filip Blagojevic

Steven William Keckler

Jennifer M Haddox

Gregory M Kapfhammer

Abdulrahman Mahmoud

Ryan Colyer

Yangxiang Huang

Systems and methods for detecting hardware faults in computer-based feedback control systems. Multiple instances of the system control program(s) are run on system processors. System sensor data are input to each instance, and the control commands output by each instance are compared. As instantiations of the same programs receive largely the same sensor data, differences between output commands may indicate the presence of one or more hardware faults.

Hardware fault detection for feedback control systems in autonomous machine applications

An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

System and methods for hardware-software cooperative pipeline error detection

Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

Adversarial scenarios for safety testing of autonomous vehicles

A packed error correction code (ECC) technique opportunistically embeds ECC check-bits with compressed data. When compressed, the data is encoded in fewer bits and is therefore fragmented when stored or transmitted compared with the uncompressed data. The ECC check-bits may be packed with compressed data at 'source' points. The check-bits are transmitted along with the compressed data and, at any 'intermediate' point between the source and a &#x201c;destination&#x201d; the check-bits may be used to detect and correct errors in the compressed data. In contrast with conventional systems, packed ECC enables end-to-end coverage for sufficiently-compressed data within the processor and also externally. While storage circuitry typically is protected by structure-specific ECC, protection is also beneficial for data as it is transmitted between processing and/or storage units.

Packed error correction code (ECC) for compressed data protection

Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.

Tensor-based driving scenario characterization

A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Apparatus and method for low power low latency high capacity storage class memory

Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.

Optimizing software-directed instruction replication for GPU error detection

A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.

Approaches for retrieving files from a replicated file system. A component receives, from a requestor, a request for a copy of a data unit. The component identifies a plurality of storage nodes that each stores a complete copy of the data unit. The component sends, to the plurality of storage nodes, an instruction to retrieve a copy of the data unit within a specified period of time. At each storage node receiving an instruction, a determination of whether the copy of the data unit may be retrieved within the specified period of time is made, and if so, the copy of the data unit is provided to the component only if the copy of the data unit was actually retrieved within the specified period. The component provides the first copy of the data unit it receives to the requestor and discards any subsequently received copies of the data unit.

Deadline-based scheduling in a distributed file system

A method and a storage system are provided for implementing a sustained large block random write performance mechanism for shingled magnetic recording (SMR) drives in a redundant array of inexpensive disks (RAID). A Solid State Drive (SSD) is provided with the SMR drives in the RAID. The SSD is used in a hot spare mode, which is activated when a large block random-write event is identified for a SMR drive in the RAID. In the hot spare mode, the SSD temporarily receives new incoming writes for the identified SMR drive. Then the identified SMR drive is updated from the SSD to restore the state of the identified SMR drive, and operations continue with normal writing only using the SMR drives in the RAID.

Implementing large block random write hot spare SSD for SMR RAID

A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.

Method and structure enabling improved native command queueing in a data storage device

A shingled magnetic recording hard disk drive that uses writeable cache tracks in the inter-band gaps between the annular data bands minimizes the effect of far track erasure (FTE) in the boundary regions of annular data bands caused by writing to the cache tracks. Based on the relative FTE effect for all the tracks in a range of tracks of the cache track being written, a count increment (CI) table or a cumulative count increment (CCI) table is maintained. For every writing to a cache track, a count for each track in an adjacent boundary region, or a cumulative count for each adjacent boundary region, is increased. When the count value for a track, or the cumulative count for a boundary region, reaches a predetermined threshold the data is read from that band and rewritten to the same band.

Shingled magnetic recording disk drive with inter-band disk cache and minimization of the effect of far track erasure on adjacent data bands

A shingled magnetic recording (SMR) hard disk drive (HDD) essentially eliminates the effect of far track erasure (FTE) in the boundary regions of annular data bands caused by writing in the boundary regions of adjacent annular data bands. The extent of the FTE effect is determined for each track within a range of tracks of the track being written. Based on the relative FTE effect for all the tracks in the range, a count increment (CI) table or a cumulative count increment (CCI) table is maintained for all the tracks in the range. For every writing to a track in a boundary region, a count for each track in an adjacent boundary region, or a cumulative count for the adjacent boundary region, is increased. When the count reaches a predetermined threshold the data is read from that band and rewritten to the same band.

Shingled magnetic recording disk drive with minimization of the effect of far track erasure on adjacent data bands

Growing community of inventors

Alviso, CA, United States of America

Timothy Tsai