Intrinsity, Inc.

Timothy S Leight

Terence M Potter

James S Blomgren

A design tool to support design of a N-NARY logic circuit is described. The designer develops a syntax statement that comprises encoded information according to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the N-NARY logic circuit and the specific configuration of transistors required to build the N-NARY logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the N-NARY circuit and a physical circuit description of the N-NARY circuit.

Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation

A design tool to support design of logic circuits is described. The designer develops a syntax statement that comprises encoded information to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the logic circuit and the specific configuration of transistors required to build the logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the logic circuit and a physical circuit description of the logic circuit.

Method and apparatus for a logic circuit design tool

A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.

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Austin, TX, United States of America

Timothy S Leight