Mips Computer Systems, Inc.

Silicon Graphics, Incorporated

Timothy S Fu

Paul M Farmwald

David Zhang

A system and method for distributing data in a system. The system comprises a control register logic circuits located at scattered locations in the system, where a location is defined as scattered if the propagation delay of data sent from the control register is more than approximately one clock period. The system also comprises one or more shift registers coupled to the control register and the logic circuits. A section of each shift register is placed in proximity to each logic circuit and data is shifted serially from the control register through the shift registers to the logic circuits. A synchronizer circuit is coupled to the shift registers to synchronize data arriving at each section of the shift registers with a shift control signal arriving at the same section of the shift register.

Synchronization circuits for the distribution of unique data to scattered locations

A slot determination mechanism wherein a number of bus units establish their positions along the bus and the total number of units on the bus. The units are connected in a bidirectional daisy chain. A one-cycle reset pulse is sent downstream to unit 1 (the upstream unit). Each unit on receiving one or more pulses from upstream sends that many plus one pulses downstream and then sends a one pulse upstream. Each unit then transmits upstream whatever it receives from downstream. The number of pulses received from upstream provide the slot number. The total number of pulses received from upstream and downstream provide the total number of units.

Slot determination mechanism using pulse counting

Error reporting circuitry interrupts the CPU on the occurrence of a single bit memory error only when the chip member causing the error is different from the chip number that caused the previous error.

Growing community of inventors

Fremont, CA, United States of America

Timothy S Fu