Texas Instruments Corporation

Timothy Paul Duryea

Sri Navaneethakrishnan Easwaran

Vaibhav Garg

Vijayalakshmi Devarajan

Shanmuganand Chellamuthu

Benjamin Lee Amey

Kannan Soundarapandian

Lawrence James Gewax

Sri Navaneethakrishna Easwaran

One example includes a method for validating a circuit design. The method includes providing a set of coded rules. Each of the coded rules can define conditions for circuit cells to qualify the circuit design as being radiation-hardened. The method also includes accessing a circuit design netlist associated with the circuit design from a circuit design database. The method also includes evaluating each of the circuit cells in the circuit design netlist with respect to each of the coded rules. The method further includes providing a circuit evaluation report comprising an indication of failure of a set of the circuit cells with respect to one or more of the coded rules in response to the evaluation.

Circuit design validation tool for radiation-hardened design

In one example, an apparatus comprises first, second and third memory devices, an error detection circuit, and an error correction circuit. The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.

Data correction of redundant data storage

Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

Redundant analog built-in self test

An electronic control unit (ECU) operates between first and second voltage rails and includes an amplifier circuit and a single current sense circuit coupled to carry a signal to a bus pin and to protect the bus pin from both a short to ground and a short to battery. The single current sense circuit includes a switch circuit that passes the signal to the bus pin and a forward current sensing circuit that provides a second current that is proportional to an output current at the bus pin. The forward current sensing circuit causes the second current to be substantially zero when voltage on the bus pin is above a given value. The single current sense circuit also includes a forward current protection circuit and a reverse current switching circuit that receives the second current and closes a connection to the second voltage when the second current is zero.

Circuit providing reverse current protection for high-side driver

A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.

Current sink with negative voltage tolerance

The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

Diagnostic monitoring for analog-to-digital converters

An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.

Overvoltage testing apparatus

In many applications, particularly in automotive applications, integrated circuits (IC) are designed to withstand large fly-back currents from inductive loads. As these ICs have become smaller, the switching transistors (which are coupled to the inductive loads) have remained relatively large so as to withstand the fly-back currents. The size of these switching transistors has become a limiting factor in designing compact ICs. Here, an IC is provided with an adaptive clamp that allows for a significant reduction in the area of a switching transistor for an inductive load.

Growing community of inventors

Dallas, TX, United States of America

Timothy Paul Duryea