Texas Instruments Corporation

Timothy Patrick Pauletti

Amneh Mohammed Akour

Suheng Chen

Nikolaus Klemmer

Abhijit Anant Patki

Nat Maruthachalam Natarajan

Tarkesh Pande

John H Carpenter, Jr

Wayne Tien-Feng Chen

Sameer P Pendharkar

David John Baldwin

Richard K Hester

Jonathan S Brodsky

Robert Steinhoff

Chuan Ni

Jayanth Rangaraju

Ross Eliot Teggatz

Joseph A Devore

Reza Sharifi

Benjamin Lee Amey

Keliu Shu

Mark B Weaver

Timothy John Legat

Sameer Pendharker

A monitoring circuit for a photovoltaic module includes a measurement conditioning circuit, a microcontroller circuit, and a transmitter circuit. The measurement conditioning circuit includes a voltage sense terminal, a voltage reference terminal, and a digital measurement data output. The microcontroller circuit includes a digital measurement data input coupled with the digital measurement data output, a modulation clock input, a measurement data stream output, and a transmit select output. The transmitter circuit includes a measurement data stream input coupled with the measurement data stream output, a modulation clock output coupled with the modulation clock input, a transmit select input coupled with the transmit select output, and positive and negative output communication terminals.

Monitoring circuit for photovoltaic module

A DC-DC regulator system includes a power circuit which has a first input coupled to receive an input voltage, a second input coupled to receive a control signal and an output to provide a regulated output voltage. The system includes a control circuit which has a first input coupled to receive the regulated output voltage, a second input coupled to receive a reference voltage, a first output to provide the control signal, and a second output to provide a converter clock signal. The system includes an out-of-audio circuit which has a first input coupled to receive a minimum threshold frequency signal, a second input coupled to receive the converter clock signal, a third input coupled to the power circuit output, and a fourth input coupled to receive a bandwidth control clock signal.

DC-DC converter with out-of-audio circuit

A controller circuit for a PV sub-module includes a power harvest controller circuit, a voltage limit controller circuit, a power mode control circuit, a multiplexer circuit, and a switching converter circuit. The power harvest controller circuit, including a first PV voltage input, a ceiling reference input, a floor reference input, and a first gate control output. The voltage limit controller circuit, including a first output voltage feedback input, a pulse width reference input, and a second gate control output. The power mode control circuit, including a second output voltage feedback input, a mode reference input, and a mode selection output. The multiplexer circuit, including a first gate control input, a second gate control input, a mode selection input, and a third gate control output. The switching converter circuit, including a second PV voltage input, a third gate control input, and a DC voltage output.

Controller circuit for photovoltaic sub-module

A controller circuit for a PV module includes a receiver circuit and a mode control and power conversion circuit. The receiver circuit receives a first signal from a transmitter circuit and changes a second signal from a first state to a second state responsive to the first signal. The mode control and power conversion circuit receives a DC voltage from a string of PV cells, receives the second signal from the receiver circuit, switches from a first mode to a second mode in response to the second signal being in the second state, converts the DC string voltage to a standby voltage in the second mode, and provides the standby voltage to DC power lines. The standby voltage is less than an operating voltage provided by the mode control and power conversion circuit in the first mode.

Controller circuit for photovoltaic module

A controller circuit for a PV module includes a receiver circuit and a mode control and power conversion circuit. The receiver circuit receives a first signal from a transmitter circuit associated with the PV module. The receiver circuit changes a second signal from a first state to a second state based the first signal. The mode control and power conversion circuit receives a DC string voltage from a string of PV cells associated with the PV module, receives the second signal from the receiver circuit, switches from a first mode to a second mode in response to the second signal being changed to the second state, converts the DC string voltage to a standby voltage in the second mode, and provides the standby voltage to DC power lines between the PV module and a DC-to-AC inverter in the second mode.

An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith

A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.

Threshold computation circuit for S-FSK receiver, integrated circuit, and method associated therewith

Disclosed examples include integrated circuits configurable according to sensed circuit conditions to provide configurable power converter topologies with externally connected circuitry to implement buck, boost, buck-boost, low dropout and/or hot-swap power converters. The ICs include one or more sets of series connected high and low side transistors connected with corresponding IC pads to allow connection to external circuitry to form a particular power converter configuration. The IC includes a control circuit and a configuration circuit to sense a circuit condition of the IC and to configure the control circuit to provide switching control signals to the transistors to implement one of a plurality of power converter topologies.

Integrated circuit with configurable control and power switches

An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

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Dallas, TX, United States of America

Timothy Patrick Pauletti